一种无片外电容高电源抑制比LDO设计  

An Output-Capacitorless Low-Dropout Regulator with High Power Supply Rejection

作　　者：郭少威 盛祥和 卢杨 王少昊 GUO Shao-wei;SHENG Xiang-he;LU Yang;WANG Shao-hao(FZU-Jinjiang Joint Institute of Microelectronics,Fuzhou University)

机构地区：[1]福州大学晋江微电子研究院

出　　处：《中国集成电路》2024年第5期28-33,78,共7页China lntegrated Circuit

摘　　要：低压差线性稳压器(Low Dropout Regulator,LDO)电路要求低输入输出压差和高电源抑制比(Power Supply Rejection Ratio,PSRR)。本文采用前馈纹波消除电路和负电容电路实现了在低输入输出压差(≤0.2 V)条件下分别对无片外电容高电源抑制比LDO的10 KHz以下频段和1 MHz频带内的电源噪声抑制能力进行提升。此外,提出的方案还通过调整第二级误差放大器的增益,实现了级间电源噪声制约,进一步提升了电源抑制比。本文基于SMIC 55 nm工艺对提出的LDO电路进行了设计与仿真。结果表明,设计的LDO在1.8 V输入电压下可以获得稳定的1.6 V输出电压,输入输出压差≤0.2 V,在1MHz以下频段内PSRR均大于75 dB,10~100 KHz频段的积分噪声为15μV_(RMS)。此外,该LDO还实现1.43 mV/V线性调整率,负载调整率为10μV/mA,总体电路消耗静态电流为76μA。Low Dropout Regulator(LDO)circuits require low input-to-output voltage differences and high supply rejection ratios.In this paper,feed-forward ripple cancellation circuit and negative capacitance circuits are used to realize the enhancement of power supply noise rejection capability of capacitorless LDO with high power supply rejection ratio in the sub-10 KHz band and in the 1 MHz band,respectively,under low input-output voltage difference(≤0.2 V)conditions.In addition,the proposed scheme realizes inter-stage power supply noise constraints by adjusting the gain of the second stage error amplifier,which further improves the power supply rejection ratio.In this paper,the proposed LDO circuit is designed and simulated based on SMIC 55 nm process.The results show that the designed LDO achieves a stable 1.6 V output voltage at 1.8 V input voltage,an input-output voltage difference≤0.2 V,a PSRR greater than 75 dB in all frequency bands up to 1 MHz,and a noise density of 15μV_(RMS)in the 10~100 KHz band.In addition,the LDO achieves a linear tuning ratio of 1.43 mV/V,a load tuning ratio of 10μV/mA,an overall circuit consumption quiescent current of 76μA.

关 键 词：高电源抑制比 前馈纹波消除 负电容电路 无电容型LDO 

分 类 号：TM44[电气工程—电器]