Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH  

作　　者：Zhengzhou CAO Guozhu LIU Yanfei ZHANG Yueer SHAN Yuting XU 

机构地区：[1]No.58 Research Institute,China Electronics Technology Group Corporation,Wuxi 214035,China

出　　处：《Frontiers of Information Technology & Electronic Engineering》2024年第4期485-499,共15页信息与电子工程前沿（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.62174150);the Natural Science Foundation of Jiangsu Province,China(Nos.BK20211040 and BK20211041)。

摘　　要：This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.

关 键 词：Field programmable gate array(FPGA) Programmable logic element(PLE) Boolean logic operation Look-up table Sense-Switch pFLASH Threshold voltage 

分 类 号：TN402[电子电信—微电子学与固体电子学]