一种高PSRR高稳定性的LDO设计  

A LDO Design with High PSRR and High Stability

作　　者：杨煌虹 武华[1] 陈翰民 黄沥彬 曹先国 YANG Huanghong;WU Hua;CHEN Hanmin;HUANG Libin;CAO Xianguo(College of Physics and Electronic Information,Gannan Normal University,Ganzhou Jiangxi 341000,China;Sichuan Xinsheng Electronics Co.,Ltd.,Mianyang Sichuan 621000,China)

机构地区：[1]赣南师范大学物理与电子信息学院,江西赣州341000 [2]四川芯盛电子有限公司,四川绵阳621000

出　　处：《电子器件》2024年第2期344-349,共6页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(61650404);江西省教育厅科技项目(GJJ201411)。

摘　　要：提出了一种高PSRR高稳定性的低压差线性稳压器(Low Dropout Linear Regular,LDO),该LDO设计了高精度的带隙基准电路和误差放大器,并利用前馈纹波消除技术设计了电源抑制比增强模块,有效提高了电路中高频的电源抑制比(Power Supply Rejection Ratio,PSRR)。基于CSMC 0.18μm工艺对提出的LDO电路进行仿真验证,芯片面积为150μm×131μm。该LDO在4.5 V~5.5 V的输入电压范围下,稳定输出不受温度影响的2.5 V电压;于1 mA轻负载下,电源抑制比在低频处为-103.3 dB,在1 MHz处超过-60 dB。当输出电容为2.2μF时,LDO电路轻载下相位裕度为58.3°,重载下相位裕度为64.1°,具有良好的系统稳定性。A high PSRR high stability low dropout linear regular(LDO)is proposed.High precision band gap reference circuit and error amplifier are designed,feed forward ripple elimination technology is used to design the power suppression ratio enhancement module,and the high frequency power supply rejection ratio(PSRR)is effectively improved.The proposed LDO circuit is simulated based on the CSMC 0.18μm process,with a chip area of 150μm×131μm。This LDO has a stable output of 2.5 V voltage without temperature in⁃fluence at the input voltage range of 4.5 V~5.5 V,and at 1 mA light load,the power suppression ratio is-103.3 dB at low frequency and over-60 dB at 1 MHz.When the output capacitance is 2.2μF,the LDO circuit phase margin is 58.3°under light load and 64.1°under heavy load,with good system stability.

关 键 词：LDO 高PSRR 高稳定性 前馈纹波消除技术 带隙基准电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]