基于Innovus改善芯片绕线资源的电源网络布线方法  

A power network routing method based on Innovus to improve chip routing resource

作　　者：王淑芬[1] 高璐 秦贵阳 朱志强 Wang Shufen;Gao Lu;Qin Guiyang;Zhu Zhiqiang(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子技术应用》2024年第5期19-23,共5页Application of Electronic Technique

摘　　要：随着集成电路的集成度越来越高,芯片的面积越来越小,芯片内单元密度会随之增加,这将为芯片的后端物理设计带来诸多的挑战。其中芯片面积的减小直接影响布线资源,导致布线拥塞,以此造成芯片线路无法绕通以及时序和串扰的问题。提出了一种改进的电源网络的布线方法,极大提升了信号线的走线空间利用率,有效解决了高集成度芯片的短路问题。With the increasing integration of integrated circuit,the area of the chip is getting smaller and smaller,and the density of cells in the chip will increase,which will bring many challenges to the physical design of the chip.The decrease of the chip area directly affects the routing resources,leading to the congestion,and seriously causes the problem of short,and the problems of timing and crosstalk.This paper proposes an improved method of power design,which greatly improves the space utilization of signal wire,and solves the problem of short in the high integration chip.

关 键 词：物理设计 单元密度 电源规划 拥塞 

分 类 号：TN402[电子电信—微电子学与固体电子学]