一种11bit流水线高速模数转换器  

An 11 bit Pipelined High-Speed Analog-to-Digital Converter

作　　者：黄政 蔡孟冶 姜岩峰 Huang Zheng;Cai Mengye;Jiang Yanfeng(Department of Electronic Engineering,School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,China)

机构地区：[1]江南大学物联网工程学院电子工程系,江苏无锡214122

出　　处：《半导体技术》2024年第6期561-568,共8页Semiconductor Technology

基　　金：江苏省自然科学基金(BK20210453)。

摘　　要：为解决流水线模数转换器(ADC)在连续工作时功耗高、电容器匹配度有限以及运算放大器大摆幅输出信号下线性度下降的问题,基于0.5μm BCD工艺,设计了一款11 bit流水线高速ADC。提出了无采样保持放大器、幅度减半和多位量化相结合的设计方法,使ADC在大摆幅信号下有足够的线性度来处理信号,同时使电容数模转换器(DAC)的匹配精度满足ADC分辨率的要求,极大地降低了对电容阵列几何参数的匹配精度要求,具有较低的功耗。采用Cadence Virtuoso设计版图,测试结果表明,芯片的微分非线性(DNL)在-0.5~+0.5 LSB范围内,有效位数(ENOB)为10.61 bit,功耗为97 mW,获得了较好的性能。In order to solve the problems of high power consumption, limited capacitor matching, and linearity degradation under large-swing output signals of operational amplifiers in continuous operation of pipelined analog-to-digital converters(ADCs),an 11 bit high-speed pipelined analog-to-digital converter based on 0.5 μm BCD process was designed.A design method combining no sample-and-hold amplifier, amplitude halving, and multi-bit quantization was proposed to make the ADC have sufficient linearity to process signals under large-swing signals, and at the same time to make the matching accuracy of the capacitive digital-to-analog converter(DAC) meet the requirement of the ADC's resolution, which greatly reduced the requirement for the matching accuracy of the geometric parameters of the capacitive arrays, and had a low power consumption.Cadence Virtuoso was used to design the layout.And the test results show that the chip has a differential nonlinearity(DNL) range of-0.5-+0.5 LSB,an effective number of bits(ENOB) of 10.61 bit, and a power consumption of 97 mW,exhibiting good performances.

关 键 词：流水线模数转换器(ADC) 幅度减半 无采样保持 线性度 多位量化 电容失配 有效位数(ENOB) 

分 类 号：TN792[电子电信—电路与系统] TN433