基于FPGA的单光子时间数字转换器设计  

Design of time-to-digital converter based on FPGA

作　　者：何继爱[1] 辛家乐 石麟泰 He Jiai;Xin Jiale;Shi Lintai(School of Computer and Communication,Lanzhou University of Technology,Lanzhou 730050,China)

机构地区：[1]兰州理工大学计算机与通信学院,兰州730050

出　　处：《电子测量技术》2024年第5期16-21,共6页Electronic Measurement Technology

基　　金：国家自然科学基金(62361040)项目资助。

摘　　要：针对单光子计数器对高速飞行光子时间测量的高分辨率要求,传统的TDC在时间测量上存在误差较大的不足。本文设计了一种利用FPGA内部逻辑延迟单元Carry4级联构建延迟链的TDC。该方法首先使用子链平均的方式进行数据采样,避免数据“气泡”。其次,结合码密度测试和bin-by-bin校准将各级延迟单元宽度校准至接近均匀宽度,提高系统的测量精度。最后,通过Vivado软件仿真并烧录至ZYNQ7000进行板级测试,实验结果表明,该TDC能够在3 ns的动态时间范围内实现时间分辨率10.91 ps,差分非线性(DNL)范围为[-0.75,1.01]LSB,积分非线性(INL)范围为[-1.74,2.19]LSB。In view of the high-resolution requirements of single-photon counters for high-speed flight photon time measurement,the traditional time-to-digital converter TDC has the disadvantage of large errors in time measurement.This paper designs a TDC that uses the internal logic delay unit Carry4 of the FPGA to cascade to build a delay chain.The method firstly uses the method of sub chain average to sample the data and avoid the data"bubble".Secondly,the width of each delay cell is calibrated to nearly uniform width by combining the code density test and bin-by-bin calibration to improve the measurement accuracy of the system.Finally,Vivado software was simulated and burned to ZYNQ7000 for board-level testing.The experimental results show that the TDC can achieve time resolution 10.91 ps in the dynamic time range of 3 ns.DNL(DNL)range is[0.75,1.01]LSB,INL(INL)range for[1.74,2.19]LSB.

关 键 词：FPGA 时间数字转换 Carry4 码密度测试 差分非线性 积分非线性 

分 类 号：TN47[电子电信—微电子学与固体电子学]