DRFM系统中多目标长延迟数据的存储方法研究  

Research on Storage Method of Multi-Target Long Delay Data in DRFM System

作　　者：郭博 褚振勇 邢斌 马皓博 GUO Bo;CHU Zhenyong;XING Bin;MA Haobo(School of Information Engineering,Xijing University,Xi’an 710000,China;Xi’an Qingfei Electronic Technology Co.,Ltd.,Xi’an 710000,China)

机构地区：[1]西京学院电子信息学院,西安710123 [2]西安擎飞电子科技有限公司,西安710075

出　　处：《电子信息对抗技术》2024年第3期68-74,共7页Electronic Information Warfare Technology

基　　金：西安市创新能力强基计划资助项目(21XJZZ0084);陕西省自然科学基金资助项目(2022GY-118)。

摘　　要：数字射频存储器(Digital Radio Frequency Memory,DRFM)在雷达、电子对抗设备的研制、测试等领域得到了广泛关注。典型的DRFM系统由模数转换、下变频、存储、信号处理、上变频以及数模转换等模块组成。其中,存储模块决定了DRFM所能模拟的目标距离和数量,是决定DRFM性能的核心模块。现有DRFM中的数据存储器有三种:现场可编程门阵列(Field Programmable Gate Array,FPGA)片上高速Block RAM(Random Access Memory)、片外静态随机存储器(Static Random-Access Memory,SRAM)或片外双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random-Access Memory,DDR SDRAM)。片上Block RAM虽然速度快但容量非常有限,片外静态RAM容量大但价格昂贵,片外DDR存储器价格便宜但读写时序存在随机性,在DRFM系统中的应用受限。在多目标、大带宽、长延迟的应用背景下,存储器带宽、容量与成本之间的矛盾尤为突出。为了解决这个问题,通过研究DDR存储器的存储特性,提出了一种使用DDR存储器作为粗延迟器件,FPGA内部Block RAM作为精延迟器件的两级延迟方案,有效解决了全脉冲存储中目标数量、瞬时带宽与存储深度之间的矛盾。Digital radio frequency memory(DRFM) has received extensive attention in the field of radar and electronic countermeasures.A typical DRFM system consists of modules such as analog-to-digital conversion,down conversion,storage,signal processing,up conversion,and digital-to-analog conversion.Among them,the storage module determines the distance and number of targets that DRFM can simulate,and is the core module that determines the performance of DRFM.There are three types of data storage in existing DRFM:on chip high-speed Block RAM(Random Access Memory),off chip static random-access memory(SRAM) and off chip double data rate synchronous dynamic random-access memory(DDR SDRAM).On chip Block RAM is fast but has very limited capacity.Off chip SRAM has large capacity but is expensive.Off chip DDR memory is cheap but has randomness in read and write timing,which limits its application in DRFM systems.In the context of multi-objective,large bandwidth,and long latency applications,the contradiction between memory bandwidth,capacity,and cost is particularly prominent.To solve this issue,a two-stage delay scheme is proposed using DDR memory as a coarse delay device and FPGA internal Block RAM as a fine delay device by studying the storage characteristics of DDR memory,which effectively solves the contradiction between the number of targets,instantaneous bandwidth,and storage depth in full pulse storage.

关 键 词：DRFM 大带宽 多目标 DDR存储器 

分 类 号：TN974[电子电信—信号与信息处理] TN911.72[电子电信—信息与通信工程]