A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic  

作　　者：Junyao Ji Xinao Ji Ziyu Zhou Zhichao Dai Xuhui Chen Jie Zhang Zheng Jiang Hong Zhang 

机构地区：[1]School of Microelectronics,Xi'an Jiaotong University,Xi'an 710049,China [2]Qingdao Hi-image Tech.Co.Ltd.,Qingdao 266100,China

出　　处：《Journal of Semiconductors》2024年第6期3-12,共10页半导体学报（英文版）

基　　金：supported by Qingdao Hi-image Technologies Co., Ltd;in part by the NSFC of China under Grant 62174149, 61974118, 62004156;the National Key R&D Program of China under Grant 2022YFC2404902

摘　　要：This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.

关 键 词：SAR ADC control logic reference ringing DAC incomplete settling 

分 类 号：TN7[电子电信—电路与系统]