A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS  

作　　者：Yukun He Zhao Yuan Kanan Wang Renjie Tang Yunxiang He Xian Chen Zhengyang Ye Xiaoyan Gui 

机构地区：[1]School of Microelectronics,Xi’an Jiaotong University,Xi’an 710049,China

出　　处：《Journal of Semiconductors》2024年第6期35-46,共12页半导体学报（英文版）

基　　金：supported by National Natural Science Foundation of China under Grant 62174132;the Fundamental Research Funds for Central Universities under Grant xzy022022060.

摘　　要：A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.

关 键 词：transceiver(TRx) feed-forward equalizer(FFE) clock and data recovery(CDR) continuous time linear equalizer(CTLE) 

分 类 号：TN8[电子电信—信息与通信工程]