Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning  

作　　者：Chang Libo Hu Yiqing Du Huimin Wang Jihe 

机构地区：[1]School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China [2]School of Computer Science,Northwestern Polytechnical University,Xi'an 710072,China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2024年第2期72-84,共13页中国邮电高校学报（英文版）

基　　金：the National Key Research and Development Program of China(2019YFB1803600);the Key Scientific Research Program of Shaanxi Provincial Department of Education(22JY059);the China Civil Aviation Airworthiness Center Open Foundation(SH2021111903)。

摘　　要：To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.

关 键 词：quasi-cyclic low density parity check(QC-LDPC) dynamic voltage and frequency scaling(DVFS) reconfigurable computing coarse-grained reconfigurable arrays(CGRAs) 

分 类 号：TN911.22[电子电信—通信与信息系统]