基于FPGA的语义分割算法设计与实现  

Design and implementation of FPGA⁃based semantic segmentation algorithm

作　　者：汤镇铭 陶青川[1] Tang Zhenming;Tao Qingchuan(College of Electronics and Information Engineering,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学电子信息学院,成都610065

出　　处：《现代计算机》2024年第8期24-30,共7页Modern Computer

摘　　要：为解决边缘端水利检测场景中水面情况复杂且具有实时性要求的问题,对BiSeNet网络进行了改进,得到了一种基于FPGA边缘设备的轻量化的实时语义分割算法。该算法通过VitisAI对模型进行量化、Vitis软件平台软硬件协同优化设计定制了深度学习处理单元DPU,实现了基于FPGA的语义分割算法的部署。在自制水利数据集上保持较低精度损失的同时实现了良好的性能,实验结果表明,改进后的网络模型在精度上损失3.7%的情况下,在ZCU104设备上实现了31.06 FPS的推理速度,相对于ARM设备获得了18.9倍的加速推理效果。所提出的方法能够满足低功耗需求下实时水利场景分割任务的要求。To address the intricacies and real⁃time imperatives inherent in water surface detection within edge water resources monitoring scenarios,enhancements are made to the BiSeNet network,yielding a streamlined real⁃time semantic segmentation algo⁃rithm tailored for FPGA edge devices.This algorithm first undergoes model quantization via Vitis AI,followed by collaborative opti⁃mization design on the Vitis software platform,leading to the customization of a Deep Learning Processing Unit(DPU)for facilitat⁃ing the deployment of the semantic segmentation algorithm on FPGA.Evaluation on a proprietary water resources dataset demon⁃strates the algorithm’s ability to maintain commendable performance while incurring only a nominal loss in accuracy.Experimental findings reveal that the refined network model attains an inference speed of 31.06 frames per second(FPS)on the ZCU104 device,with a marginal accuracy decrement of 3.7%.This translates to an inference acceleration of 18.9 times compared to ARM devices.In summary,the proposed methodology satisfies the real⁃time segmentation requisites of water resources monitoring tasks within low⁃power constraints.

关 键 词：深度学习 语义分割 FPGA BiSeNet DPU 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]