通用CPU外部接口激励设计  

Incentive Design of Common CPU External Interface

作　　者：毛茏玮 黄博 李勇 MAO Longwei;HUANG Bo;LI Yong(Chengdu Guoxinan Information Industry Base Co.,Ltd,Chengdu,Sichuan 610041,China)

机构地区：[1]成都国信安信息产业基地有限公司,四川成都610041

出　　处：《自动化应用》2024年第10期245-250,共6页Automation Application

摘　　要：现场可编程门阵列(FPGA)软件设计愈发复杂,片间驱动的设计尤其明显。可编程逻辑器件软件测试要求中对片间驱动的测试涉及接口测试、时序测试2种常规测试类型;而部件测试和系统测试往往存在多个软件单元和模块,待测接口数量较多且分立,片间驱动的测试质量通常受接口激励设计制约。通常FPGA设计框架中会使用较多的通用CPU外部控制接口,通过统一常见通用CPU外部接口验证激励设计规范,对被测模块每个外部输入/输出接口的信息格式、数据特性等进行验证。对异步串口、同步串口、IIC、SPI、CAN、EMIF、GPMC、LOCAL BUS、PCI 9种通用CPU外部接口进行激励设计,分析了各类接口的时序及通信约束,借助QuestaSim仿真平台对相应接口进行仿真,逐项比对输出波形验证激励设计的正确性。The FPGA software is more and more complex,especially the design of chip-to-chip driver.The chip-to-chip driver testing in programmable logic device testing requirements involves both interface testing and timing testing.But there are many software units and modules in component testing and system testing.The number of interfaces to be tested is large and discrete.Therefore,the test quality of the chip-to-chip driver is usually restricted by the interface excitation design.The common CPU external control interface is usually used in the FPGA design framework.Through establishing the design specification of common CPU external interface verification,the information format and data characteristics of each external input-output interface of the tested module are verified.In this paper,nine kinds of universal CPU external interfaces,such as UART,SSI,IC,SPI,CAN,EMIF GPMC,LOCAL BUS,PCI are designed.The timing and communication constraints of various interfaces are analyzed,and the corresponding interfaces are simulated by means of QuestaSim simulation platform,and the output waveforms are compared to verify the correctness of the excitation design.

关 键 词：片间驱动 FPGA软件 通用CPU外部接口 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]