应用于24G雷达芯片系统的12 bit 50 MS/s SAR ADC  

12 bit 50 MS/s SAR ADC applied to 24G radar chip system

作　　者：张鸣 陈磊 郑喜鹏 郝建娇 ZHANG Ming;CHEN Lei;ZHENG Xipeng;HAO Jianjiao(College of Electronics and Information Engineering,Shanghai University of Electric Power,Shanghai 201306,China)

机构地区：[1]上海电力大学电子与信息工程学院,上海201306

出　　处：《电子设计工程》2024年第12期65-70,共6页Electronic Design Engineering

摘　　要：针对24G雷达芯片的设计需要,设计了一款12 bit、采样率为50 MS/s的逐次逼近型模数转换器(SARADC)。整体架构采用全差分形式,采用改进型的分裂式电容阵列,提高CDAC的建立速度。同时,采用二进制重组权重的冗余校正算法,进一步提高系统线性度。利用优化的Strong-arm比较器结构,与异步时序配合,提高ADC的工作速度。电路采用SMIC 40 nmCMOS工艺进行设计,后仿真结果表明,在电源电压为1.1 V,采样率为50 MS/s下,输入信号频率约为5 MHz的正弦信号,无杂散动态范围为80.6 dBc,信噪失真比为71.5 dB,有效位数能够达到11.58 bit。According to the design requirements of 24G radar chip,a 12 bit Successive Approximation Analog⁃to⁃Digital Converter(SAR ADC)with a sampling rate of 50 MS/s was designed.The overall architecture adopts a fully differential form,and an improved split capacitor array was used to improve the CDAC establishment speed.At the same time,the redundancy correction algorithm of binary recombination weight is adopted to further improve the linearity of the system.The comparator utilized the optimized Strong⁃arm structure and cooperates with the asynchronous timing sequence to improve the working speed of the ADC.The circuit was designed with SMIC 40 nm CMOS process.The post⁃simulation results show that when the power supply voltage was 1.1 V and the sampling rate was 50 MS/s,the frequency of the input signal was a sinusoidal signal of 5 MHz,the spurious⁃free dynamic range was 80.6 dBc,the signal⁃to⁃noise distortion ratio was 71.5 dB,and the effective number of bit of the SAR ADC was 11.58 bit.

关 键 词：逐次逼近型模数转换器 分裂式电容阵列 二进制重组权重 冗余 异步时序 

分 类 号：TN792[电子电信—电路与系统]