一种应用于12 bit SAR ADC C-R混和式DAC  

A hybrid C-R DAC applied to 12 bit SAR ADC

作　　者：谢海情[1] 陈振华 谷洪波 曹武 XIE Haiqing;CHEN Zhenhua;GU Hongbo;CAO Wu(School of Physics and Electronics Science,Changsha University of Science and Technology,Changsha 410114,China;Hunan Pinteng Electronic Technology Co.,Ltd.,Changsha 410114,China)

机构地区：[1]长沙理工大学物理与电子科学学院,湖南长沙410114 [2]湖南品腾电子科技有限公司,湖南长沙410114

出　　处：《电子设计工程》2024年第12期113-117,共5页Electronic Design Engineering

摘　　要：针对ADC中功耗、精度与成本之间相互制约的问题,提出一种应用于12 bitSARADC的混合电容电阻型(C-R)DAC结构。高6位采用温度计编码的电容阵列结构;低6位选择电阻阵列结构。对电路进行非线性分析选取合理的元件尺寸。另外,采用非交叠时钟电路作为开关控制时序,避免开关切换时引起瞬态毛刺导致电容电荷泄露。基于GSMC 95 nm工艺,完成电路、版图设计与仿真,并完成流片测试,DAC版图总面积为317.2μm×262.5μm,流片测试结果表明,DNL的范围为-0.38~+0.44 LSB,INL的范围为-0.73~+0.4 LSB,满足12位ADC的设计要求。A hybrid capacitance resistance(C-R)DAC architecture for 12 bit SAR ADC is proposed to address the mutual constraints between power consumption,accuracy,and cost in ADC.The high 6 significant bits adopt a thermometer coded capacitive array structure.Low 6 significant bit selective resistor array structure.Select a reasonable component size through nonlinear analysis of the circuit.In addition,a non⁃overlapping clock circuit is used as the switching control timing to avoid causing transient burrs and capacitive charge leakage during switching.Based on the GSMC 95 nm process,complete circuit and layout design and simulation,and complete chip testing.The total DAC layout area is 317.2μm×262.5μm,the flow sheet test results show that the range of DNL is-0.38~+0.44 LSB,and the range of INL is-0.73~+0.4 LSB,meeting the design requirements of a 12 bit ADC.

关 键 词：数模转换器 逐次逼近型 电容电阻结构 温度计编码 

分 类 号：TN492[电子电信—微电子学与固体电子学]