SOT-MRAM读电路泄电结构优化  

The optimization of discharge structure in read circuit for SOT-MRAM

作　　者：王超 吴晨烨 叶海波 陆楠楠 李嘉威 孙杰杰[1] WANG Chao;WU Chen-ye;YE Hai-bo;LU Nan-nan;LI Jiawei;SUN Jie-jie(China Electronics Technology Group Corporation No.58 Research Institute)

机构地区：[1]中国电子科技集团公司第五十八研究所

出　　处：《中国集成电路》2024年第6期43-47,共5页China lntegrated Circuit

摘　　要：自旋轨道矩磁性随机存储器(SOT-MRAM)作为第四代磁随机存储器广受关注。SOT-MRAM为三端结构,应用于2T2R结构时,不对称写入容易导致电荷积累,从而对读产生影响,甚至导致读取错误的发生。因此研究针对SOT-MRAM特点的读电路泄电结构,减小写入对读取通路的影响具有重要意义。本文针对SOT-MRAM写入不对称导致电荷积累问题,对比了两种泄电电路结构,有效降低了首个读周期的读取时间延迟。研究了引入的泄电结构对位线电容的容忍度的影响。分析了位线电容差异导致读取不对称的机理,结合首个读周期读取时间延迟问题,提出了适合SOT-MRAM特点的读取电路泄电结构。本文的研究为SOT-MRAM读取电路的设计提供了新思路。Spin-orbit torque magnetic random memory(SOT-MRAM),as the fourth generation of magnetic random memory,has attracted much attention.When the SOT-MRAM with a three-terminal structure is applied to 2T2R structure,asymmetric writing process tends to result in the accumulation of charge,which has negative effects on the reading process,and even leads to read errors.Therefore,it is of great significance to study the discharge structure in read circuit for the SOT-MRAM to reduce the impact of writing on the read path.In this paper,we compare two types of discharge circuit structures for SOT-MRAM with respect to the problem of charge accumulation due to asymmetric writing,which effectively reduces the read time delay of the first read cycle.The effect of the introduced discharge structures on the tolerance of bit line capacitance is investigated.The mechanism of read asymmetry due to the difference in bit line capacitance is analyzed,and a read circuit discharge structure suitable for the SOT-MRAM is proposed in consideration of the problem of read time delay in the first read cycle.The work provides new ideas for the design of SOT-MRAM read circuits.

关 键 词：自旋轨道矩磁随机存储器 读电路 泄电 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]