一种宽延时范围的压控延时线电路  

A wide delay range voltage control delay line circuit

作　　者：吴贵洲 谭勋琼[1] 白创 WU Gui-zhou;TAN Xun-qiong;BAI Chuang(School of Physics and Electronic Science,Changsha University of Science&Technology)

机构地区：[1]长沙理工大学物理与电子科学学院

出　　处：《中国集成电路》2024年第6期61-66,89,共7页China lntegrated Circuit

摘　　要：为改善压控延时线(voltage control delay line,VCDL)的延时性能,用于满足延时锁相环(delay locked loop,DLL)在不同频率时钟下的工作需求,设计并实现了一种宽延时范围的压控延时线电路。该电路通过在偏置电路增加多条配置路径生成宽范围输出电流,增大基本延时单元充放电电流的范围;通过在基本延迟单元增加一个可选电容负载,进一步拓宽延迟时间范围。基于40nm CMOS工艺和1.1 V电源电压进行仿真,VCDL所占物理版图面积为0.004mm2。版图后仿真结果表明该VCDL能提供2.2~391ns的延迟,使得DLL可以工作在3~400MHz的输入频率范围。通过引入可配置结构的VCDL,为宽锁定范围的DLL系统提供了新的解决思路。In order to improve the delay performance of voltage control delay line(VCDL)and meet the working requirements of delay locked loop(DLL)under different frequency clocks,a voltage-controlled delay line circuit with wide delay range is designed and implemented.The circuit generates a wide range of output current by adding multiple configuration paths to the bias circuit,and increases the range of charge and discharge current of the basic delay unit.The delay time range is further widened by adding an optional capacitive load to the basic delay unit.Based on 40nm CMOS process and 1.1 V power supply,the physical area of VCDL is 0.004 mm2.The post-layout simulation results show that the VCDL can provide 2.2~391ns delay,so that the DLL can work in the input frequency range of 3~400MHz.By introducing the configurable VCDL,it provides a new solution for the DLL system with wide locking range.

关 键 词：压控延时线 延时性能 延时锁相环 延时时间范围 可配置 

分 类 号：TN47[电子电信—微电子学与固体电子学]