基于UVM的总线桥接模块验证  

Bus Bridge Module Verification Based on UVM

作　　者：毛国栋 郭涛[1] 梁颖 陈梦凡 石帅 MAO Guodong;GUO Tao;LIANG Ying;CHEN Mengfan;SHI Shuai(State Key Laboratory of Electronic Measurement Technology,North University of China,Taiyuan 030051;China Academy of Launch Vehicle Technology,China Aerospace Science and Technology Corporation,Beijing 100000)

机构地区：[1]中北大学电子测试技术国家重点实验室,太原030051 [2]中国航天科技集团有限公司中国运载火箭技术研究院,北京100000

出　　处：《舰船电子工程》2024年第3期160-164,186,共6页Ship Electronic Engineering

基　　金：国家自然科学基金项目(编号:51975541)资助。

摘　　要：随着集成电路工艺与设计水平的进步,集成电路规模和复杂度大幅提升,采用传统的验证方法已经很难满足芯片开发对于功能验证的需求。论文在UVM验证方法学的基础上,开展针对系统级芯片中的总线桥接模块的验证研究工作。首先对该模块的功能特性和接口信号展开分析,完成了UVM验证平台的搭建,然后编写测试用例对模块的所有功能点进行测试,根据测试结果对设计进行修改。在全部测试用例通过后开展回归测试,回归测试结果显示代码覆盖率达到98%,功能覆盖率达到100%,达到验证要求。经过该次验证,该模块自身的功能得到了充分验证,可成功应用于系统级芯片的片内互联,同时该次所搭建验证平台具有一定的通用性和可复用性。With the progress of integrated circuit technology and design level,the scale and complexity of integrated circuit have been greatly increased,so it is difficult to meet the requirements of functional verification in chip development by using tradi-tional verification methods.Based on the UVM verification methodology,this paper studies the verification of bus bridge module in system-level chip.Firstly,the functional features and interface signals of the module are analyzed,and the UVM verification plat-form is built.Then,test-cases are written to test all functional points of the module,and the design is modified according to the test results.The regression test is carried out after all test cases passed.The regression test results showes that code coverage reached 98%and function coverage reached 100%,meeting the verification requirements.After this verification,the function of the module has been fully verified,and can be successfully applied to the on-chip interconnection of system-level chips.Meanwhile,the verifi-cation platform built in this time has certain universality and re-usability.

关 键 词：集成电路 功能验证 UVM AMBA 可重用性 

分 类 号：TN4[电子电信—微电子学与固体电子学]