检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:王鹏 李子航 范毓洋 WANG Peng;LI Zihang;FAN Yuyang(College of Safety Science and Engineering,Civil Aviation University of China,Tianjin 300300,China)
机构地区:[1]中国民航大学安全科学与工程学院,天津300300
出 处:《电讯技术》2024年第6期973-978,共6页Telecommunication Engineering
基 金:国家重点研发计划(2021YFB1600600);中央高校基本科研业务费项目(XJ2021003601)。
摘 要:静态随机存储器(Static Random Access Memory, SRAM)型现场可编程门阵列(Field Programmable Gate Array, FPGA)广泛应用于航空航天系统中,但是高空中FPGA易受高能粒子影响造成配置出错,互联资源上发生的单点错误可能导致跨域故障,使芯片内多个模块同时失效。跨域故障可能导致电路中的工作模块与检错模块同时故障,使设备中存在不能被检测到的隐蔽故障。针对上述问题,提出在芯片上将不同功能的模块相互隔离,并通过约束实现模块间可信通信的故障隔离方法,将故障限定在单一模块内,防止多个模块同时失效,提高电路的容错能力。通过故障注入评估隔离设计前后的航空电子全双工交换式以太网(Avionics Full Duplex Switched Ethernet, AFDX)电路的各类故障发生率。实验结果证明隔离设计可以与电路原有的检错容错机制结合,将隐蔽故障的发生率降为原来的3%。Static random access memory(SRAM)type field programmable gate array(FPGA)is widely used in aerospace and astrospace systems,but high-altitude FPGAs are vulnerable to high-energy particles that can cause configuration errors,and single-point errors in interconnect resources can lead to cross-domain failures that can cause multiple modules within the chip to fail simultaneously.Cross-domain errors can lead to the simultaneous fault of both a working module and an error detection module in the circuit,leaving a hidden fault in the device that cannot be detected.In view of above problems,a fault isolation method is proposed,in which modules with different functions are isolated from each other on the chip,and trusted communication between modules is realized through constraints.The fault is limited to a single module,preventing multiple modules from failing at the same time,and improving the fault tolerance of the circuit.The occurrence rate of various faults in avionics full duplex switched Ethernet(AFDX)circuits before and after the isolation design is evaluated by fault injection.Experiments show that the isolation design can be combined with the original error detection and fault tolerance mechanism of the circuit to reduce the occurrence rate of hidden faults to 3%.
分 类 号:TN79[电子电信—电路与系统]
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:216.73.216.200