基于半绝缘SiC衬底GaN HEMT体陷阱的效应分析  

Analysis of GaN HEMT Bulk Trap Effect Based on Semi Insulating SiC Substrate

作　　者：牛梓戌 NIU Zixu(School of Electrical Engineering,Zhejiang University,Zhejiang 310027,China)

机构地区：[1]浙江大学电气工程学院,浙江310027

出　　处：《电子技术（上海）》2024年第3期1-3,共3页Electronic Technology

摘　　要：阐述采用背栅测试来表征GaN-on-SiC HEMT的体陷阱效应,过程中分别表现出两段式特征,分别对应Ⅲ族氮化物缓冲层以及半绝缘SiC衬底的加压过程。另外在Silvaco TCAD平台搭建相应的物理模型,仿真体陷阱效应以及在不同衬底电压下的电势分布。This paper describes the use of back gate testing to characterize the volume trap effect of Ga N on Si C HEMT, which exhibits a two-stage characteristic corresponding to the pressurization process of the Ⅲ nitride buffer layer and semi insulating Si C substrate. In addition, a corresponding physical model is built on the Silvaco TCAD platform to simulate the volume trap effect and potential distribution under different substrate voltages.

关 键 词：GaN HEMTs 半绝缘SiC衬底 背栅测试 体陷阱效应建模 电流坍塌 外延优化 

分 类 号：TN405[电子电信—微电子学与固体电子学]