Research and design of matrix operation accelerator based on reconfigurable array  

作　　者：邓军勇 ZHANG Pan JIANG Lin XIE Xiaoyan DENG Jingwen DENG Junyong;ZHANG Pan;JIANG Lin;XIE Xiaoyan;DENG Jingwen(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,P.R.China;School of Computer Science and Technology,Xi’an University of Science and Technology,Xi’an 710054,P.R.China;School of Computer,Xi’an University of Posts and Telecommunications,Xi’an 710121,P.R.China)

机构地区：[1]School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,P.R.China [2]School of Computer Science and Technology,Xi’an University of Science and Technology,Xi’an 710054,P.R.China [3]School of Computer,Xi’an University of Posts and Telecommunications,Xi’an 710121,P.R.China

出　　处：《High Technology Letters》2024年第2期128-137,共10页高技术通讯（英文版）

基　　金：the National Key R&D Program of China(No.2022ZD0119001);the National Natural Science Foundation of China(No.61834005);the Shaanxi Province Key R&D Plan(No.2022GY-027);the Key Scientific Research Project of Shaanxi Department of Education(No.22JY060);the Education Research Project of Xi'an University of Posts and Telecommunications(No.JGA202108);the Graduate Student Innovation Fund of Xi’an University of Posts and Telecommunications(No.CXJJYL2022035).

摘　　要：In the case of massive data,matrix operations are very computationally intensive,and the memory limitation in standalone mode leads to the system inefficiencies.At the same time,it is difficult for matrix operations to achieve flexible switching between different requirements when implemented in hardware.To address this problem,this paper proposes a matrix operation accelerator based on reconfigurable arrays in the context of the application of recommender systems(RS).Based on the reconfigurable array processor(APR-16)with reconfiguration,a parallelized design of matrix operations on processing element(PE)array is realized with flexibility.The experimental results show that,compared with the proposed central processing unit(CPU)and graphics processing unit(GPU)hybrid implementation matrix multiplication framework,the energy efficiency ratio of the accelerator proposed in this paper is improved by about 35×.Compared with blocked alternating least squares(BALS),its the energy efficiency ratio has been accelerated by about 1×,and the switching of matrix factorization(MF)schemes suitable for different sparsity can be realized.

关 键 词：matrix factorization(MF) recommender system(RS) array processor RECONFIGURABLE matrix multiplication 

分 类 号：TP391.3[自动化与计算机技术—计算机应用技术]