可扩展架构的超大点数FFT处理器设计  

Design of Ultra Large Points FFT Processor with Scalable Architecture

作　　者：王江 吴佳 WANG Jiang;WU Jia(V&G Information System Co.,Ltd.,Shanghai 201702,China)

机构地区：[1]上海威固信息技术股份有限公司,上海201702

出　　处：《现代雷达》2024年第5期54-59,共6页Modern Radar

基　　金：上海市协同创新资助项目(2020-jmrh1-kj2)。

摘　　要：面向合成孔径雷达、遥感、电子对抗等领域研究了一款高性能的超大点数快速傅里叶变换(FFT)处理器。文中提出了一种可扩展架构,即针对不同的应用场景可以动态实时调整FFT算法的基数以及处理点数;存储器划分为16个存储模块,可以通过产生无冲突地址进行访问,输出与输入数据帧可以共享同一存储器,具备高效存储器特征。FFT运算采用并行流水线排布,当采用高基算法时,可高并行度访问存储器,实现并行计算,从而获得明显的实时性优势。FFT各级运算采用循环移位寄存器产生地址,以保证蝶算单元输入数据的抽取间隔,并在最后一级输出时进行循环移位寄存器反转操作产生地址,实现输入输出共享存储器。所提设计方法规整、高效、适用范围广泛,便于现场可编程逻辑器件以及集成电路实施,并且也将持续受益于存储器工艺的提升。The high performance ultra large sequence fast Fourier transformation(FFT)processor for the synthetic aperture radar,remote sensing,and electronic countermeasure applications is presented in this paper.A scalable architecture is proposed which can dynamically adjust the FFT radices and points.The memory is divided to 16 banks which can be accessed by the conflict-free address.The input frame and output fame share the same memory,showing memory-efficient feature.The parallel pipeline arrangement is adopted by the FFT computation.When the high radices is adopted,the memory can be accessed with high parallelism and the parallel computation is realized,resulting in obvious real time advantage.The address is generated by the circular and shift register in every stage to guarantee the decimation distance of data fed to the butterfly unit.At the last stage,the circular and shift register is reversed to generate address,resulting in the same memory can be shared by the input and output data.The proposed design method is unified,efficient,general,and friendly for the implementation of the field programmable gate array and very large scale integration.The design will be benefited from the memory fabrication technique enhancement continuously.

关 键 词：快速傅里叶变换 并行计算 可扩展架构 高效存储器 流水线 

分 类 号：TN492[电子电信—微电子学与固体电子学]