采用Mash2-1架构的高精度Sigma-Delta ADC设计  

Design of a High-Precision Sigma-Delta ADC Using Mash2-1 Architecture

作　　者：于凯至 辛晓宁[1] 任建[1] 卢苡 YU Kaizhi;XIN Xiaoning;REN Jian;LU Yi(School of Information Science and Engineering,Shenyang University of Technology,Shenyang 110870,China)

机构地区：[1]沈阳工业大学信息科学与工程学院,沈阳110870

出　　处：《微处理机》2024年第3期22-25,共4页Microprocessors

摘　　要：鉴于模数转换器(ADC)在芯片和混合信号处理领域举足轻重的作用,为探索进一步提高模数转换器精度的可能性,满足当今应用系统对模数转换精度的新需求,设计一款基于Mash2-1级联架构的sigma-delta ADC。设计采用TSMC 180 nm CMOS工艺,在完成调制器电路的同时,使用Verilog代码方式实现了配套的误差消除以及数字抽取滤波器。对调制器进行了建模及非理想因素的分析,并通过使用斩波调制技术等手段对电路的非理想性进行优化。经仿真验证,结果表明,本设计在3.3 V电源、27℃工作环境、TT典型工艺条件下,表现出优异的信噪比,总谐波失真等性能指标也较理想,适用于高精度、低失真的应用场合。In view of the critical role of analog-to-digital converter(ADC)in the field of chip and mixed-signal processing,a sigma-delta ADC based on Mash2-1 cascade architecture is designed to explore the possibility of further improving the accuracy of ADC and meet the new requirements of contemporary application systems.TSMC 180 nm CMOS process is adopted in the design.While completing the modulator circuit,Verilog code is used to realize the matching error elimination and digital decimation filter.The modulator is modeled and the non-ideal factors are analyzed,and the non-ideal of the circuit is optimized by using chopper modulation technology.The simulation results show that the design has excellent signal-to-noise ratio and ideal performance indexes such as total harmonic distortion under 3.3 V power supply,27℃working environment and TT typical process conditions,and is suitable for high-precision and low-distortion applications.

关 键 词：SIGMA-DELTA调制器 高信噪比 低失真 Mash级联架构 

分 类 号：TN402[电子电信—微电子学与固体电子学]