扇出型晶圆级封装重布线层互联结构失效分析  

Failure analysis of interconnect structure in redistribution layer of fan-out wafer level packaging

作　　者：范懿锋 明雪飞[2] 曹瑞 王智彬[1] 孟猛 FAN Yifeng;MING Xuefei;CAO Rui;WANG Zhibin;MENG Meng(China Aerospace Components Engineering Center,Beijing 100098,China;The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi 214035,China)

机构地区：[1]中国航天宇航元器件工程中心,北京100098 [2]中国电子科技集团第58研究所,无锡214035

出　　处：《集成电路与嵌入式系统》2024年第7期43-47,共5页Integrated Circuits and Embedded Systems

摘　　要：本文研制了一批不同尺寸规格的扇出型晶圆级封装结构的菊花链测试芯片样品,对不同几何参数下的样品进行了温度循环试验,并通过金相显微镜、扫描电镜和能谱分析等手段对失效样品进行了失效分析,研究总结了扇出型晶圆级封装重布线层互联结构的失效模式。研究工作可为扇出型晶圆级封装产品的可靠性评估和高可靠应用提供指导。In this study,a series of fan-out wafer-level packaging daisy chain test chips with various dimensions and specifications were fabricated.Temperature cycling tests were conducted on samples under different geometric parameters.Failure analysis of the failed samples was performed using techniques such as metallographic microscopy,scanning electron microscopy(SEM),and energy-dispersive X-ray spectroscopy(EDS).The failure modes of the redistribution layer interconnect structures in fan-out WLP were systematically investigated and summarized.This research provides guidance for reliability evaluation and high-reliability applications of fan-out WLP products.

关 键 词：扇出型晶圆级封装 可靠性 失效分析 重布线层 

分 类 号：TN47[电子电信—微电子学与固体电子学]