具有快速再锁定特性的亚采样锁相环设计  

Design of a Sub-Sampling Phase-Locked Loop with Fast Relocking Characteristics

在线阅读下载全文

作  者:赵毅强 叶泽宇 叶茂 宋毅恒 段文浩 李尧 Zhao Yiqiang;Ye Zeyu;Ye Mao;Song Yiheng;Duan Wenhao;Li Yao(School of Microelectronics,Tianjin University,Tianjin 300072,China;Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology,Tianjin 300072,China;National Key Laboratory of Electromagnetic Space Security,Tianjin 300308,China)

机构地区:[1]天津大学微电子学院,天津300072 [2]天津市成像与感知微电子技术重点实验室,天津300072 [3]电磁空间安全全国重点实验室,天津300308

出  处:《天津大学学报(自然科学与工程技术版)》2024年第7期711-720,共10页Journal of Tianjin University:Science and Technology

基  金:国家电网有限公司总部管理科技资助项目(5700-202041397A-0-0-00).

摘  要:相较于传统的电荷泵锁相环,亚采样锁相环以其优良的带内噪声抑制作用,近年来得到了关注和研究.但传统的亚采样锁相环由于其辅助锁频环路中三态鉴频鉴相器较长的固定死区,一旦受到干扰失锁后,需要较长的再锁定时间.针对这一问题,本文在传统的亚采样锁相环设计基础上,设计了一种低噪声、短死区的整数分频亚采样锁相环电路架构,其包含了核心亚采样环路、辅助锁频环路.在辅助锁频环路把输出信号频率锁定至预设频率附近后,环路切换至亚采样环路.亚采样环路通过亚采样鉴相器实现低频参考时钟对高频输出时钟的采样,并将参考时钟和输出时钟之间的相位差转化为输出电压差;该输出电压差控制亚采样电荷泵对环路滤波器充放电,调节输出时钟频率和相位.双环路之间的切换通过辅助锁频环路中的短死区鉴相器实现,这使锁相环既避免了长死区导致的长再锁定时间,也避免了分频器额外的带内噪声放大作用,在兼顾亚采样锁相环良好的带内噪声抑制性能的基础上,有效提高了电路的鲁棒性.本文基于180 nm 1P6M CMOS工艺,完成了800 MHz输出频率的整数分频亚采样锁相环的电路设计、版图绘制和后仿真验证.核心电路版图面积为0.114mm2,功耗为10.8 mW.仿真结果表明,所设计的亚采样锁相环相较于传统结构将再锁定时间降至1.18μs,同时带内相位噪声为-117dBc/Hz@200kHz,参考杂散为57.8 dBc-.Compared with conventional charge pump phase-locked loops,sub-sampling phase-locked loops have recently attracted attention owing to their low in-band noise.However,because of the long dead zone of the tri-state phase frequency detector in the auxiliary frequency-locked loop,the conventional sub-sampling phase-locked loop may require a long relocking time once it is unlocked by disturbances.To address this problem,this study presents the circuit architecture of a low-noise,short-dead-zone integer-N sub-sampling phase-locked loop based on the conventional sub-sampling phase-locked loop design.The new design incorporates core sub-sampling and auxiliary frequency-locked loops.After the auxiliary frequency-locked loop locks the output frequency to a preset frequency,it switches to the sub-sampling loop.The sub-sampling loop uses the lower frequency reference clock to sample the higher frequency output clock through the sub-sampling phase detector and converts the phase difference between the reference and output clocks into the output voltage difference.The output voltage difference controls the sub-sampling charge pump to charge or discharge the loop filter to regulate the output clock frequency and phase.Switching between the dual loops is achieved through a phase detector with a short dead zone in the auxiliary frequency-locked loop.This approach helps the phase-locked loop avoid the long relocking time caused by the long dead zone and the additional in-band noise amplification of the divider.Consequently,it effectively enhancesthe robustness of the circuit while considering the low in-band noise of the sub-sampling phase-locked loop.Herein,circuit design,layout,and post-simulation verification of an 800 MHz integer-N sub-sampling phase-locked loop were accomplished using the 180 nm 1P6M CMOS process.The core circuit layout area is 0.114mm2,and the power consumption is 10.8 mW.The simu-lation results show that the designed sub-sampling phase-locked loop reduces the relocking time to 1.18μs compared to the convent

关 键 词:亚采样锁相环 短死区 再锁定时间 

分 类 号:TN911.8[电子电信—通信与信息系统]

 

参考文献:

正在载入数据...

 

二级参考文献:

正在载入数据...

 

耦合文献:

正在载入数据...

 

引证文献:

正在载入数据...

 

二级引证文献:

正在载入数据...

 

同被引文献:

正在载入数据...

 

相关期刊文献:

正在载入数据...

相关的主题
相关的作者对象
相关的机构对象