一种高速多级全差分放大器设计  

A design of a high-speed multi-stage fully differential amplifier

作　　者：沈念一 秦雷[1,2] 周三博 SHEN Nianyi;QIN Lei;ZHOU Sanbo(School of Applied Science,Beijing Information Science&Technology University,Beijing 100192,China;Key Laboratory of Sensors,Beijing Information Science&Technology University,Beijing 100192,China)

机构地区：[1]北京信息科技大学理学院,北京100192 [2]北京信息科技大学传感器重点实验室,北京100192

出　　处：《电子元件与材料》2024年第5期603-611,共9页Electronic Components And Materials

基　　金：国家自然科学基金(U2006218);北京市属高等学校高水平科研创新团队建设支持计划项目(BPHR20220124)。

摘　　要：设计了一款基于互补双极工艺的高带宽和低噪声全差分放大器,可实现全差分或单端转差分功能。提出了一种H型桥式输入结构,可实现高摆率、低失真;此外,放大器通过内部共模反馈环路将共模信号反馈到两个增益级,实现差分输出共模电平的调整,使高速全差分放大器特别适合于高速高精度模数转换器(ADC)输入信号的缓冲和放大。放大器内部跨导线性环为AB类输出级提供有效偏置,减小输出级失真的同时提供高动态范围。基于EDA工具进行了放大器电路和版图设计,后仿结果表明,在±5 V电源供电下,放大器-3 dB带宽达到366 MHz,压摆率大于1150 V/μs,输入电压噪声小于10nV/√Hz,输入失调电压在±1 mV内。A high-bandwidth low-noise fully differential amplifier was proposed with complementary bipolar technology,which can realize fully differential or single-ended-to-differential conversion.A novel H-bridge input structure was proposed to achieve a high slew rate and low distortion.Furthermore,the amplifier utilized an internal common-mode feedback loop to feedback the common-mode signal to two gain stages,enabling adjustment of the differential output's common-mode level.This feature made the high-speed,fully differential amplifier particularly suitable for buffering and amplifying the input signals of high-speed and high-precision analog-to-digital converters(ADCs).The amplifier incorporated a transconductance linearization loop in the Class AB output stage,providing effective biasing to reduce distortion and ensure a high dynamic range.The circuit and layout design of the amplifier were performed using EDA tools.The post-layout simulation results show that with a±5 V power supply,the amplifier achieves a-3 dB bandwidth of 366 MHz,a slew rate greater than 1150 V/μs,an input voltage noise below 10nV/√Hz,and an input offset voltage within±1 mV.

关 键 词：双极型 全差分 高摆率 高速 共模反馈 

分 类 号：TN722[电子电信—电路与系统]