3.125 Gb/s自适应模拟均衡器设计  

Design of 3.125 Gb/s Adaptive Analog Equalizer

作　　者：李雪[1] 李野[1] LI Xue;LI Ye(School of Physics,Changchun University of Science and Technology,Changchun 130022)

机构地区：[1]长春理工大学物理学院,长春130022

出　　处：《长春理工大学学报（自然科学版）》2024年第3期10-16,共7页Journal of Changchun University of Science and Technology(Natural Science Edition)

基　　金：国家自然科学基金(U2141239)。

摘　　要：采用标准0.18μm CMOS工艺,设计了一种3.125 Gb/s自适应模拟均衡器。其中,均衡滤波器模块采用了一种新颖的有源负反馈结构,可以有效提高均衡滤波器的带宽和增益补偿范围。自适应控制环路采用包含截割电路的单回路结构,通过检测信号的斜率以产生不同的调节电压来调整均衡滤波器的高频增益值,从而能够对不同长度的信道进行自适应补偿。由仿真结果可知,在3.125 Gb/s和4 Gb/s两种数据速率下,输出信号的抖动值为0.24 UI和0.31 UI。在1.562 5 GHz和2 GHz处可均衡的信道损耗分别为13.04~22.04 dB和16.94~28.50 dB,均衡后信号的输出摆幅为270 mV。在1.8 V电源电压下,测得电路的总功耗为59.4 mW。A 3.125 Gb/s adaptive analog equalizer is designed in a standard 0.18μm CMOS process.A novel active negative feedback structure is adopted to improve the bandwidth and gain compensation range of the equalization filter.The adaptive control loop employs a single-loop structure including a slicer,which adjusts the high-frequency gain by detecting the slope of the signal to generate different adjustment voltages,so that the channels of different lengths can be adaptively compensated.It can be seen from the results that the jitter of output signals are 0.24 UI and 0.31 UI at 3.125 Gb/s and 4 Gb/s.The channel losses that can be compensated 13.04~22.04 dB and 16.94~28.50 dB at 1.5625 GHz and 2 GHz,and the output swing of the equalized signals are 270 mV.Under 1.8 V supply voltage,the total power consumption is 59.4 mW.

关 键 词：模拟均衡器 自适应控制环路 有源负反馈 斜率检测 

分 类 号：TN432[电子电信—微电子学与固体电子学]