优化LZW压缩算法的FPGA硬件实现  

FPGA Hardware Implementation of Optimized LZW Compression Algorithm

作　　者：严承启 李锦明[1] YAN Chengqi;LI Jinming(School of Semiconductor and Physics,North University of China,Taiyuan 030051)

机构地区：[1]中北大学半导体与物理学院,太原030051

出　　处：《舰船电子工程》2024年第4期111-114,177,共5页Ship Electronic Engineering

基　　金：装发基础研究项目(编号:514010504-308)资助。

摘　　要：LZW算法其软件实现速度较慢,占用CPU资源过多,不适合对实时性有要求的场景,针对这一问题,论文提出了基于FPGA的LZW压缩算法硬件实现,通过确定字典大小,优化字典更新,减少了搜索时间和占用内存。并使用Kintex-7系列FPGA XC7K160T进行硬件加速处理,极大地提高了数据压缩速度和效率。实验结果表明,该硬件实现在压缩速率上平均达到386 Mb/s,是软件的9.66倍,压缩速率、实时性等方面均优于传统软件实现的LZW算法。This article proposes a hardware implementation of the LZW compression algorithm based on FPGA to address the slow software implementation speed and excessive CPU resource consumption,which is not suitable for scenarios with real-time re⁃quirements.By determining the size of the dictionary and optimizing dictionary updates,search time and memory usage are reduced.The Kintex-7 series FPGA XC7K160T is used for hardware acceleration processing,greatly improving data compression speed and efficiency.Experimental results show that the hardware implementation achieves an average compression rate of 386 Mb/s,which is 9.66 times faster than software,and is superior to traditional software implementations of the LZW algorithm in terms of compression rate and real-time performance.

关 键 词：LZW算法 FPGA 压缩性能 实时性 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]