基于交叉开关互连的多核堆栈处理器架构设计  

Architecture design of multicore stack processor based on crossbar interconnection

作　　者：刘欢庆 周永录 刘宏杰[1,2] 代红兵 LIU Huan-qing;ZHOU Yong-lu;LIU Hong-jie;DAI Hong-bing(School of Information Science and Engineering,Yunnan University,Kunming 650500,China;Digital Media Technology Key Laboratory of Universities in Yunnan,Yunnan University,Kunming 650223,China)

机构地区：[1]云南大学信息学院,云南昆明650500 [2]云南大学云南省高校数字媒体技术重点实验室,云南昆明650223

出　　处：《计算机工程与设计》2024年第7期2212-2219,共8页Computer Engineering and Design

基　　金：国家自然科学基金项目(61962060)。

摘　　要：为满足堆栈处理器对于并行化程序应用的需求,提出一种多核堆栈处理器架构。在单核堆栈处理器的基础上,以交叉开关作为核间互连结构,通过对指令集、高速缓存器、一致性协议以及中断机制的设计,可在一个时钟周期内完成取指、译码、执行、核间数据传输和中断响应操作。在Xilinx FPGA芯片上进行单核、双核和四核堆栈处理器的实现,通过矩阵乘法计算进行性能实验验证,在100 MHz时钟频率的情况下,四核堆栈处理器的最大性能相当于单核堆栈处理器的3.99倍。实验结果表明,基于交叉开关互连的多核堆栈处理器架构可较好发挥多核堆栈处理器中每一个核心的性能。To meet the requirement of stack processor for parallel program application,a multi-core stack processor architecture was proposed.Based on the single-core stack processor,a crossbar switch was used as the inter-core interconnection structure.Through the design of the instruction set,cache,coherence protocol and interrupt mechanism,the instruction fetching,decoding,execution,data transfer between cores and interrupt response operations were completed.The single-core,dual-core and quad-core stack processors were implemented on Xilinx FPGA chips,and the performance experiments were verified by matrix multiplication calculation.In the case of 100 MHz clock frequency,the maximum performance of the quad-core stack processor is 3.99 times better than that of single-core stack.Experimental results show that the multi-core stack processor architecture based on the crossbar interconnection can better exert the performance of each core in the multi-core stack processor.

关 键 词：堆栈处理器 多核处理器 交叉开关 高速缓存 一致性协议 中断控制器 现场可编程门阵列 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]