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作 者:Yang Yang Lee Zaini Abdul Halim Mohd Nadhir Ab Wahab Tarik Adnan Almohamad
机构地区:[1]School of Electrical and Electronic Engineering,Universiti Sains Malaysia,Nibong Tebal 14300 Penang Malaysia [2]School of Computer Sciences,Universiti Sains Malaysia,Gelugor,11800 Penang,Malaysia [3]Electrical-Electronics Engineering Department,Faculty of Engineering,Karabuk University,78050 Karabuk,Turkiye
出 处:《Research》2024年第2期55-79,共25页研究(英文)
基 金:supported in part by the Universiti Sains Malaysia under Grant RUI 1001/PELECT/8014152.
摘 要:Stochastic computing(SC)has a substantial amount of study on application-specific integrated circuit(ASIC)design for artificial intelligence(AI)edge computing,especially the convolutional neural network(CNN)algorithm.However,SC has little to no optimization on field-programmable gate array(FPGA).Scaling up the ASIC logic without FPGA-oriented designs is inefficient,while aggregating thousands of bitstreams is still challenging in the conventional SC.This research has reinvented several FPGA-efficient 8-bit SC CNN computing architectures,i.e.,SC multiplexer multiply-accumulate,multiply-accumulate function generator,and binary rectified linear unit,and successfully scaled and implemented a fully parallel CNN model on Kintex7 FPGA.The proposed SC hardware only compromises 0.14%accuracy compared to binary computing on the handwriting Modified National Institute of Standards and Technology classification task and achieved at least 99.72%energy saving per image feedforward and 31?more data throughput than modern hardware.Unique to SC,early decision termination pushed the performance baseline exponentially with minimum accuracy loss,making SC CNN extremely lucrative for AI edge computing but limited to classification tasks.The SC's inherent noise heavily penalizes CNN regression performance,rendering SC unsuitable for regression tasks.
关 键 词:HARDWARE Highly RENDERING
分 类 号:TP183[自动化与计算机技术—控制理论与控制工程]
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