一种高可靠性IP设计的机理研究及设计实现  

One Solution for High Reliable IP Design and Research

作　　者：潘中平 PAN Zhong-ping(LYG Semiconductor Inc.)

机构地区：[1]上海凌云阁芯片科技有限公司

出　　处：《中国集成电路》2024年第7期45-49,共5页China lntegrated Circuit

摘　　要：本文是基于一种实现高可靠性IP设计的物理机理研究,首先探究了影响高可靠性IP设计的物理机理一方面来源于电迁移EM现象造成的“硬伤”,进而探讨了可用来衡量高可靠性IP的平均无故障时间MTTF的计算公式,并据此分析了对应芯片制程工艺演进的EM加剧效应。再者通过实验分析手段考察了影响高可靠性IP设计的噪声因素,界定其属于影响可靠性IP设计的“软伤”,从应对软噪声的角度提出了采用不同于常规的高电压(HV)设计方案,来实现改善高标准单元库IP设计的可靠性,进而提出一种实现高可靠性IP设计的可行方案,这一方案同时具有减小漏电流效果。This article probes and studies the physical mechanism of EM(Electromigration)between metal layers of one finished IC(Integrated Circuits)when it has been power-on for some time.Which could be one of the causes to impact high reliability design of an IP circuit,and it belongs to one kind of“hard error”indeed.In addition,it also studies the MTTF formula applicable to this phenomenon while analysis of experimental data is provided to illustrate its effect as IC manufacturing process evolves.On the other hand,it also probes the impact of noise to high reliable IP design as a kind of“soft error”,furthermore,it also proposes a kind of high voltage(HV)design solution to improve high reliability of IP design,which also has the benefit to reduce leakage current.

关 键 词：电迁移 小山包(形状)阻塞物 标准单元库 低压差线性稳压器 

分 类 号：TN402[电子电信—微电子学与固体电子学]