用于GEM-TPC探测器读出芯片的10 bit20 MSPS SAR ADC设计  

The Design of a 10 Bit 20 MSPS SAR ADC of the Readout Chip for GEM-TPC Detector

作　　者：孙志坤 千奕[1,2,3] 杨鸣宇 佘乾顺 赵红赟[1,2,3] 蒲天磊 陆伟建[1,3] 刘政强 张家瑞 SUN Zhikun;QIAN Yi;YANG Mingyu;SHE Qianshun;ZHAO Hongyun;PU Tianlei;LU Weijian;LIU Zhengqiang;ZHANG Jiarui(Institute of Modern Physics,Chinese Academy of Sciences,Lanzhou 730000,China;Advanced Energy Science and Technology Guangdong Laboratory,Huizhou 516000,China;School of Nuclear Science and Technology,University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院近代物理研究所,兰州730000 [2]先进能源科学与技术广东省实验室,惠州516000 [3]中国科学院大学核科学与技术学院,北京100049

出　　处：《电子科技大学学报》2024年第4期481-486,共6页Journal of University of Electronic Science and Technology of China

基　　金：国家自然科学基金(11975293)。

摘　　要：随着大面积气体电子倍增器——时间投影室探测器的不断发展,其对读出电子学的密度和集成度要求越来越高。基于180 nm的CMOS工艺设计完成了一款10 bit、20 MSPS的逐次逼近寄存器型模数转换器原型芯片。利用该芯片结合模拟前端模块和数字信号处理器,可实现全数字化的前端读出专用集成电路用于GEM-TPC的读出。该ADC主要由DAC模块、动态比较器模块、异步时钟生成模块和SAR逻辑模块构成。仿真结果表明,输入信号频率为1.836 MHz时,ENOB为8.61 bit,内核功耗约为3.3 mW/Ch。With the continuous development of large-area gas electron multiplier-time projection chamber detectors,the density and integration of readout electronics are increasingly required.In this paper,a 10 bit,20 MSPS successive approximation register analog-to-digital converter prototype chip is designed and fabricated by 180 nm CMOS process.Combining the SAR ADC chip with an analog front-end module and a digital signals processor,a fully digital front-end readout application specific integrated circuit for GEM-TPC is realized.The ADC is mainly composed of the DAC module,the dynamic comparator module,the asynchronous clock generation module and the SAR logic module.Simulation results show that when the input signal frequency is 1.836 MHz,the effective number of bits is 8.61 bit,and the core power consumption is about 3.3 mW/Ch.

关 键 词：GEM-TPC ASIC SAR ADC 自举开关 动态比较器 异步SAR逻辑 

分 类 号：TN492[电子电信—微电子学与固体电子学]