应用于数字隔离器高速低功耗编解码技术  

High⁃speed and low⁃power codec technology applied to digital isolators

作　　者：熊张良 陈苏婷[1] 宣志斌[2] 赵庭晨 XIONG Zhangliang;CHEN Suting;XUAN Zhibin;ZHAO Tingchen(School of Electronics and Information Engineering,Nanjing University of Information Engineering,Nanjing 210044,China;The 58th Research Institute of China Electronics Technology Corporation,Wuxi 214000,China)

机构地区：[1]南京信息工程大学电子与信息工程学院,江苏南京210044 [2]中国电子科技集团公司第五十八研究所,江苏无锡214000

出　　处：《电子设计工程》2024年第16期27-32,38,共7页Electronic Design Engineering

基　　金：国家自然科学基金资助项目(62272234)。

摘　　要：基于一种三层片上变压器隔离传输方式,设计了一款全新的应用于数字隔离器的编解码技术,采用脉冲信号调制技术方法将上升沿调制成一个正脉冲和一个负脉冲,下降沿调制成一个单正脉冲,解码侧分为两路信号,分别接收同名端和异名端信号,两路信号反相且对地差分,结合抗干扰电路排除对地干扰脉冲后滤除负脉冲,通过双D触发器还原信号,结合仿真数据得出编解码电路静态电流分别降至435 pA和398 pA,动态功耗最高为817μA,脉宽失真小于1 ns,延时小于10 ns,最高可达200 Mb/s的数据传输速率。Based on a three⁃layer on⁃chip transformer isolation transmission method,a novel encoding and decoding technology for digital isolators has been designed.The rising edge is modulated into a positive pulse and a negative pulse using pulse signal modulation technology,and the falling edge is modulated into a single positive pulse.The decoding side is divided into two signals,receiving signals from the same and different ends.The two signals are inverted and differential to the ground.By combining anti⁃interference circuits to eliminate ground interference pulses and filter out negative pulses,the signal is restored through a dual D trigger.Based on simulation data,the static current of the encoding and decoding circuit is reduced to 435 pA and 398 pA,respectively,with a maximum dynamic power consumption of 817μA.Pulse width distortion is less than 1 ns,delay is less than 10 ns,and data transmission speed can reach up to 200 Mb/s.

关 键 词：片上变压器 数字隔离器 高速率 低功耗 低延时 

分 类 号：TN432[电子电信—微电子学与固体电子学]