一种应用于音频的可重构Σ-Δ连续时间调制器  

ReconfigurableΣ-ΔContinuous-Time Modulator for Audio Applications

作　　者：罗育豪 韦保林[1] 岳宏卫[1] LUO Yuhao;WEI Baolin;YUE Hongwei(Guangxi Key Lab.of Precision Naviga.Technol.and Applic.,Guilin Univ.of Elec.Technol.,Guilin,Guangxi 541004,P.R.China)

机构地区：[1]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林541004

出　　处：《微电子学》2024年第2期183-188,共6页Microelectronics

基　　金：国家自然科学基金项目(12064003,62364009);广西自然科学基金项目(2021JJA170081)。

摘　　要：基于180 nm CMOS工艺,设计了一种应用于音频领域的可重构前馈式3阶Σ-Δ连续时间调制器。传统Σ-Δ连续时间调制器只有一种工作模式,而该设计利用可重构的积分器使Σ-Δ连续时间调制器具有高精度和低功耗两种工作模式。此外,采用的加法器提前技术减小了调制器功耗,负电阻补偿技术提高了调制器的SNDR,额外环路延时补偿技术提高了调制器的稳定性。仿真结果表明,在20 kHz信号带宽、1.8 V电源电压下,低功耗模式下调制器的SNDR为94.7 dB,功耗为291μW;高精度模式下调制器的SNDR为108 dB,功耗为436.6μW。Based on a 180 nm CMOS process,a sigma-delta continuous-time modulator with reconfigurable feedforward third-order operation was designed for audio applications.The traditional sigma-delta continuous time modulator has only one operating mode,but the proposed modulator with the reconfigurable integrator has two operating modes:high-resolution and low-power consumption modes.In addition,summation ahead is used to reduce the power consumption of the modulator,negative-R compensation is used to improve the SNDR of the modulator,and excess loop delay compensation is used to improve the stability of the modulator.With a signal bandwidth of 20 kHz and supply voltage of 1.8 V,the modulator has an SNDR of 94.7 dB and power consumption of 291μW in the low-power consumption mode and an SNDR of 108 dB and power consumption of 436.6μW in the high-resolution mode.

关 键 词：连续时间 可重构 Σ-Δ调制器 高精度 

分 类 号：TN432[电子电信—微电子学与固体电子学]