超高速数据采集及分析平台的设计与验证  

Design and Validation of Ultra-High-Speed Data Acquisition and Analysis Platform

作　　者：张续莹 刘漾 彭祖国 徐德凯 伍江雄 魏亚峰 陈超 王聪 温显超 王健安 俞宙 ZHANG Xuying;LIU Yang;PENG Zuguo;XU Dekai;WU Jiangxiong;WEI Yafeng;CHEN Chao;WANG Cong;WEN Xianchao;WANG Jianan;YU Zhou(China and National Key Laboratory of Electromagnetic Space Security,Chengdu 610000,P.R.China;Chongqing GigaChip Technology Co.Ltd.,Chongqing 400060,P.R.China)

机构地区：[1]电磁空间安全全国重点实验室,成都610000 [2]重庆吉芯科技有限公司技集团公司,重庆400060

出　　处：《微电子学》2024年第2期323-329,共7页Microelectronics

摘　　要：设计并实现了超高速数据采集及分析平台,由FPGA数据采集激励板卡、测试分析软件和PC机构成,该系统用于JESD204C接口协议的模数转换器(ADC)和数模转换器(DAC)的测试分析。从元器件选型、PCB设计与仿真、激励和软件测试三个方面进行平台的搭建,以保证平台能够在JESD204C协议的传输速率下稳定运行。基于该平台对一款6 GSPS双通道16位ADC和12 GSPS四通道16位DAC芯片进行动态性能测试,测试结果显示,ADC的SNR为56.3 dBFS,DAC的SFDR为65.5 dBFS,性能指标与手册值接近,表明该数据采集平台的功能与性能得到验证,可推广至JESD204C接口协议的其他芯片的测试,具备一定的通用性。Design and implement a ultra-high-speed data acquisition and analysis platform,consisting of FPGA data acquisition excitation boards,test analysis software,and PCs.This system is used for the testing and analysis of analog-to-digital converters(ADC)and digital-to-analog converters(DAC)using the JESD204C interface protocol.The platform is constructed from three aspects:component selection,PCB design and simulation,excitation,and software testing to ensure stable operation of the platform at the transmission rate of the JESD204C protocol.Based on this platform,dynamic performance tests were conducted on a 6 GSPS dual-channel 16 bit ADC and a 12 GSPS four-channel 16 bit DAC chip.The test results show that the SNR of the ADC is 56.3 dBFS,and the SFDR of the DAC is 65.5 dBFS,with performance indicators close to the manual values,indicating that the functionality and performance of the data acquisition platform have been verified and can be extended to testing other chips using the JESD204C interface protocol,demonstrating a certain degree of versatility.

关 键 词：采集激励板卡 JESD204C 模数转换器 数模转换器 测试与应用 

分 类 号：TN792[电子电信—电路与系统] TP274.2[自动化与计算机技术—检测技术与自动化装置]