渐变沟道全耗尽SOI MOSFET漏致势垒降低效应研究  

The drain induced barrier lowering effect of the fullydepleted SOI MOSFET with graded channel

作　　者：张冰哲 辛艳辉[1] ZHANG Bing-zhe;XIN Yan-hui(School of Electrical and Electronic Engineering,North China University of Water Resources and Electric Power,Zhengzhou 450046,Henan,China)

机构地区：[1]华北水利水电大学电子工程学院,河南郑州450046

出　　处：《宝鸡文理学院学报（自然科学版）》2024年第2期57-60,66,共5页Journal of Baoji University of Arts and Sciences(Natural Science Edition)

基　　金：国家自然科学基金项目(U2241221)。

摘　　要：目的 集SOI MOSFET(绝缘衬底上的硅金属氧化物半导体场效应晶体管)器件结构与渐变沟道的优点于一体,提出渐变沟道全耗尽SOI MOSFET器件结构,以提高MOSFET器件的微观物理性能。方法 分别列出沟道不同掺杂浓度的2个区域的泊松方程并求解,建立阈值电压模型。依据计算结果,详细分析沟道高掺杂区的掺杂浓度和掺杂长度、栅氧化层的介电常数、硅膜厚度等物理参数对漏致势垒降低(DIBL)效应的影响。结果 DIBL随沟道高掺杂区的掺杂浓度的增大而变小,随掺杂长度的减小而变小,随栅氧化层的介电常数的增大而变小,随硅层厚度减薄而变小。结论 渐变掺杂沟道结构能够有效抑制器件的DIBL。该研究结果不仅对器件的理论研究有一定的意义,而且对器件的设计提供了一定的参考价值。Purposes—To propose the device structure of a fully depleted silicon-on-insulator metal-oxide-semiconductor field effect transistor(SOI MOSFET)with graded channel,which combines the advantages of SOI MOSFET device structure and graded channel,for the purpose of improving the micro physical performance of MOSFET devices.Methods—A threshold voltage model is established by solving the Poisson equation in the both doping regions.Based on the calculation results,the effects of physical parameters,such as the doping concentration and doping length of the higher doping region,the gate-oxide dielectric constant and the silicon film thickness,on the drain induced barrier lowering(DIBL)effect are analyzed in detail.Results—DIBL decreases with the increae of doping concentration and the decrease of doping length in the high doping region of the channel,the increase of gate-oxide dielectric constant,and decrease in the thickness of silicon layer.Conclusions—The structure of graded channel can effectively suppress the DIBL.The results not only offer the physical insight into device physics,but also provide the important value for the device design.

关 键 词：渐变沟道 金属氧化物半导体场效应晶体管 漏致势垒降低 短沟道效应 

分 类 号：TN386[电子电信—物理电子学]