应用于低功耗模/数转换器的低电源电压时间域比较器  

Low supply voltage time-domain comparators for low power analog-to-digital converters

作　　者：蓝宏健 杨建行 王霖伟 李振 周荣 刘术彬 LAN Hongjian;YANG Jianhang;WANG Linwei;LI Zhen;ZHOU Rong;LIU Shubin(School of microelectronics,Xidian University,Xi’an 710071,China)

机构地区：[1]西安电子科技大学微电子学院,西安710071

出　　处：《集成电路与嵌入式系统》2024年第8期7-13,共7页Integrated Circuits and Embedded Systems

基　　金：中央高校基本科研业务费专项基金资助(XJSJ230460)。

摘　　要：针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(Time Amplifier,TA)成功实现了相位积累速度的指数级增加,有效减小了输入信号相位脱离鉴相器的“死区”所需的振荡周期数,缩短了比较延迟,优化了比较的速度和功耗。该比较器基于65 nm CMOS工艺进行设计,在0.4 V电源电压下功耗仅5.24 nW,失调电压为5.99 mV。To address issues of large delay and high power consumption in the Successive Approximation Analog-to-Digital Converter(SAR ADC)voltage-domain comparator,a-low-power-time-domain-comparator is designed in this paper.By introducing a high-gain Time Amplifier(TA),the comparator achieved an exponential increase in phase accumulation speed.This effectively reducing the number of oscillation cycles required for the input signal phase to exit the"dead zone"of the phase discriminator,thereby shortening the comparison delay and optimizing the speed and power consumption.The comparator is designed based on a 65 nm CMOS process and consumes only 5.24 nW at 0.4 V supply voltage and 5.99 mV offset voltage.

关 键 词：SAR ADC 时间域比较器 时间放大器 SR锁存器 鉴相器 

分 类 号：TN43[电子电信—微电子学与固体电子学]