基于TSMC180nm工艺的8位电压型数模转换器设计  

Research on the Design of 8-bit Voltage-based Digital to Analog Converter(DAC)Based on TSMC180 nm Process

作　　者：胡含涛 高超嵩 孙向明 朴红光 Hu Hantao;Gao Chaosong;Sun Xiangming;Piao Hongguang(College of Science,China Three Gorges University,Yichang 443000;Key Laboratory of Quark and Lighton Physics,School of Physical Science and Technology,Central China Normal University,Ministry of Education,Wuhan 430079;College of Science,Yanbian University,Yanji 133002)

机构地区：[1]三峡大学理学院,湖北宜昌443000 [2]华中师范大学物理科学与技术学院夸克与轻子物理教育部重点实验室,湖北武汉430079 [3]延边大学理学院,吉林延吉133002

出　　处：《中阿科技论坛（中英文）》2024年第8期96-102,共7页China-Arab States Science and Technology Forum

基　　金：科技部重点研发项目“基于硅像素的内径迹探测器合作研制”(2020YEE0202002)。

摘　　要：基于TSMC180nm的1P6M标准互补金属氧化物半导体(CMOS)工艺,文章设计了一款8位分辨率的R-2R阶梯架构电压型数模转换器(DAC)。为了降低电阻失配对DAC性能的影响,该DAC采用了传输门结构开关,并通过后仿真与实际测试对其性能进行了对比分析。测试结果表明,在1.8V电源供电下,总版图面积为820μm×820μm,DAC总功耗为91.8μW,其最大转换速率达250M采样次数/s,微分非线性误差(D_(NL))和积分非线性误差(I_(NL))的最大绝对值分别为0.32LSB和0.52LSB。Based on TSMC 180 nm 1P6M standard complementary metal oxide semiconductor(CMOS)process,this article proposes an 8-bit resolution R-2R ladder architecture voltage-based DAC.In order to alleviate the impact of resistance mismatch on the performance of DAC,a transmission gate structure switch was adopted,and its performance was analyzed and compared through post simulation and testing.The test results show that under a 1.8V power supply,the total layout area is 820μm×820μm,total power consumption of the DAC is 91.8μW,and its maximum conversion rate reaches 250 M sampling times/s.The maximum absolute values of differential nonlinear error(D_(NL))and integral nonlinear error(I_(NL))are 0.32 LSB and 0.52 LSB,respectively.

关 键 词：数模转换器 8位分辨率 180nm工艺 R-2R阶梯型 

分 类 号：TM4[电气工程—电器]