多线并行轨道电路电容耦合干扰机理研究  

Research on the Mechanism of the Capacitive Coupling Interference of Multiline Parallel Track Circuits

作　　者：傅宗纯[1] 李捷[1] FU Zongchun;LI Jie(Hunan Railway Professional Technology College,Zhuzhou,Hunan Province,412001 China)

机构地区：[1]湖南铁道职业技术学院,湖南株洲412001

出　　处：《科技资讯》2024年第12期60-62,共3页Science & Technology Information

基　　金：湖南省教育厅科学研究项目“高铁车站轨道电路邻线干扰机理及一体化在线监测系统研究”(项目编号:23C0809)。

摘　　要：高速铁路车站并行股道多,应用场景复杂,在三线并行情况下,中间股道易受两旁线路的电磁干扰影响。当2条线路均与中间股道同向时,中间股道所受电容耦合干扰为2条线路干扰之和,且邻线耦合电容越大,干扰亦越强。为减少多线并行邻线间的电容耦合干扰,可采取改变线路相对布局、采用屏蔽等设计措施,确保高速铁路车站轨道电路工作的稳定性和可靠性。There are many many parallel station tracks in high-speed railway stations with complex application sce-narios,and in the case of three parallel lines,the middle station track is susceptible to electromagnetic interference from the two side lines.When the two lines are in the same direction as the middle track,the capacitive coupling interference received by the middle station track is the sum of interference from the two lines,and the larger the coupling capacitance of adjacent lines,the stronger interference.In order to reduce the capacitive coupling interfer-ence among adjacent lines in the case of multiple parallel lines,design measures such as changing the relative layout of lines and adopting shielding can be taken to ensure the stability and reliability of the operation of track circuits in high-speed railway stations.

关 键 词：高速铁路 多线并行 轨道电路 邻线干扰 电容耦合 

分 类 号：P135[天文地球—天体力学]