A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS  

作　　者：Shubin LIU Chenxi HAN Xiaoteng ZHAO Yuhao ZHANG Shixin LI Hongzhi LIANG Lihong YANG Zhangming ZHU 

机构地区：[1]Key Laboratory of Analog Integrated Circuits and Systems(Ministry of Education),School of Integrated Circuits,XidianUniversity,Shaanxi71007l,China

出　　处：《Science China(Information Sciences)》2024年第8期343-344,共2页中国科学（信息科学）（英文版）

基　　金：supported by National Key Research and Development Program of China(Grant No.2022YFB4401904);National Natural Science Foundation of China(Grant Nos.62374126,62021004,62227816)。

摘　　要：With the growing demand for communication bandwidth,transmitters(TXs)are operating at higher rates,compressing thetiming margin for the last 4:1 or 2:1 multiplexer(MUX).To alleviate the timing constraints,the retimer is introduced before the last-stage MUX.However,owing to process,voltage,and temperature(PVT)variations,the phase relationship between the retiming clock and the input data is uncertain,leading to insufficient setup and hold time for the successive retimer.Therefore,the retiming clock adjustment techniques are proposed to optimize the timing margin[1,2].In this study,an adaptive retiming clock selection scheme based on the phase rotator(PR)and inverse-PRbased phase detector(PD)is proposed for high-speed transmitters,ensuring rapid convergence while reducing hardware overhead.

关 键 词：INVERSE OPTIMIZATION timing 

分 类 号：TN830[电子电信—信息与通信工程]