基于FPGA的CAN总线加密系统设计  

Design of CAN bus encryption system based on FPGA

作　　者：杨云[1] 丁鹏鸽 韩浩壮 徐知遥 刘洁 YANG Yun;DING Pengge;HAN Haozhuang;XU Zhiyao;LIU Jie(School of Information Engineering,Chang’an University,Xi’an 710064,China)

机构地区：[1]长安大学信息工程学院,陕西西安710064

出　　处：《电子设计工程》2024年第17期11-15,共5页Electronic Design Engineering

基　　金：陕西省工业攻关项目(2022GY-030)。

摘　　要：CAN总线作为应用最为广泛的车载通信总线,其数据以明文传输的特性,提升了车内通信效率的同时,也增加了信息泄露并被篡改的风险。对此,文中提出了基于国密SM3算法的车载CAN总线数据加密方式,利用FPGA硬件设备实现车载信息的收集、处理、加密、通信和控制,以满足在不降低总线通信效率的前提下,提升车载通信的安全性。根据设计要求,采用软硬件结合的方式对该方案进行了验证,实验结果表明,以SM3算法加密时,在Quartus 13.0平台上最高时钟频率可达94.7 MHz,吞吐量约为757.6 Mbit/s,造成约0.67μs的时延,达到设计目的。As the most widely used vehicle communication bus,CAN bus has the feature of data transmission in plain text,which improves the efficiency of vehicle communication,but also increases the risk of information leakage and tampering.In this regard,the paper proposes the data encryption mode of CAN bus based on Chinese password SM3 algorithm,and uses FPGA hardware device to realize the collection,processing,encryption,communication and control of vehicle information,so as to meet the premise of improving the security of vehicle communication without reducing the efficiency of bus communication.According to the design requirements,the scheme is verified by the combination of hardware and software.The experimental results show that:in the process of SM3 algorithm encryption,the maximum clock frequency can reach 94.7 MHz and the throughput is about 757.6 Mbit/s on Quartus 13.0 platform,resulting in about 0.67μs delay,which meets the design purpose.

关 键 词：硬件加密 CAN总线 SM3算法 FPGA 

分 类 号：TN918[电子电信—通信与信息系统]