应用于SAR ADC的低压瞬态强化LDO  

Design of low voltage transient enhanced LDO for SAR ADC

作　　者：林首全 陈磊 LIN Shouquan;CHEN Lei(College of Electronics and Information Engineering,Shanghai University of Electric Power,Shanghai 201306,China)

机构地区：[1]上海电力大学电子与信息工程学院,上海201306

出　　处：《电子设计工程》2024年第17期83-87,共5页Electronic Design Engineering

摘　　要：为提升采样频率为2 MHz的12 bits ADC的性能,在TSMC40 nm工艺中设计了一种用于提供基准电压的瞬态强化低压差稳压器(LDO)。误差放大器采用附加动态偏置的折叠共源共栅放大器结构,用于在大负载时加大带宽,提升增益。瞬态强化电路,使用微分器加推挽放大器的组合向功率管栅极提供快速抽灌电流,同时兼具频率补偿功能,节省补偿电容面积。再附加一个比较器控制的电流镜电路,直接调控输出电压的过冲值。加快瞬态期间大信号恢复过程。该LDO基于TSMC40 nm工艺,结果表明,在50 pF负载电容,1.1 V电源电压下,该LDO可以稳定驱动0到25 mA的负载,瞬态输出电压峰峰值在60 mV以内,整体功耗112μA。In order to improve the performance of 12 bit ADC with 2 MHz sampling frequency,a transient enhanced low⁃dropout voltage regulator(LDO)is designed to provide reference voltage in TSMC40 nm process.The error amplifier adopts a foldable cascode amplifier structure with additional dynamic bias,which is used to increase bandwidth and improve gain during heavy loads.The transient enhancement circuit uses the combination of differentiator and push⁃pull amplifier to provide fast pumping current to the gate parasitic capacitance of power transistor,and also has the frequency compensation function to save the area of compensation capacitance.In addition,a current mirror circuit controlled by a comparator is added to directly regulate the overshoot value of the output voltage.Accelerate the process of large signal recovery during transient periods.The LDO is based on the TSMC40 nm process,and the results show that under a 50 pF load capacitor and a 1.1 V power supply voltage,the LDO can stably load 0 to 25 mA,with a transient output voltage peak to peak within 60 mV,the overall power consumption is 112μA.

关 键 词：快速响应LDO 瞬态增强 动态偏置 过冲抑制 

分 类 号：TN792[电子电信—电路与系统]