基于UVM的加解扰模块验证  

UVM verification of scrambling-descrambling module

作　　者：耿正 林靖杰 田艳兵 GENG Zheng;LIN Jingjie;TIAN Yanbing(Qingdao University of Technology,Qingdao,Shandong 266002,China;Chengdu Branch,Jiangsu Xinsheng intelligent Technology Co.,Ltd.,Chengdu 610000,China)

机构地区：[1]青岛理工大学信息与控制工程学院,山东青岛266002 [2]江苏芯盛智能科技有限公司成都分公司,成都610000

出　　处：《计算机应用文摘》2024年第15期132-134,共3页Chinese Journal of Computer Application

摘　　要：基于UVM验证方法学,文章构建了一个针对NAND闪存主控芯片中加解扰模块的验证平台。该验证平台能够对加解扰模块进行全面的功能验证,并具备基本的复位验证功能,不仅能满足常规激励的需求,还能实现激励的随机化。此外,该验证平台具有一定的复用性和扩展性,能够通过扩展task和基本testcase来满足新的验证需求。Based on the UVM verification methodology,this article constructs a verification platform for verifying the scrambling module in NAND flash memory control chips.This verification platform is capable of conducting comprehensive functional verification of the encryption and decryption modules,and has basic reset verification capabilities.This verification platform not only meets the needs of conventional incentives,but also enables randomization of incentives.In addition,the verification platform has certain reusability and scalability,and can adapt to new verification requirements by extending tasks and basic test cases.

关 键 词：UVM nand flash 加解扰 芯片 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]