高密度标准延迟线研制及定值研究  

Study on the Development and Characterization of High Density Standard Delay Line

作　　者：许孟杰 顾翼[2] XU Mengjie;GU Yi(Hubei Science and Technology College,Wuhan 430074,China;Wuhan Digital Engineering Institute,Wuhan 430205,China)

机构地区：[1]湖北科技职业学院,武汉430073 [2]武汉数字工程研究所,武汉430205

出　　处：《宇航计测技术》2024年第3期17-22,共6页Journal of Astronautic Metrology and Measurement

摘　　要：延迟时间是数字集成电路测试误差的重要来源,传统单根标准延迟线对测试系统进行校准的方法,已无法满足测试系统高达数百测试通道的计量要求。针对测试系统传输延迟时间高效准确测量的需求,提出了一种基于微带线结构的高密度标准延迟线集成及定值思路,设计了4种规格的高密度标准延迟线,实现了单规格标准板上512路标准延迟线的高密度集成,提升了标准器具的便携性,提高了测试系统计量效率;设计了基于时域反射技术的标准延迟线定值方法,通过多组对比试验验证,测量结果偏差小于50 ps,延迟线满足测试系统现场计量需求。Transmission Delay is an important source of testing errors in digital integrated circuits.The traditional method of calibrating a testing system with a single standard delay line can no longer meet the metrological requirements of testing systems with hundreds of test channels.A high-density standard delay line integration and setting method based on microstrip line structure is proposed to meet the demand for efficient and accurate measurement of transmission delay time in testing systems.Four specifications of high-density standard delay lines are designed,achieving high-density integration of 512 standard delay lines on a single specification standard board,improving the portability of standard instruments and improving the measurement efficiency of testing systems;A standard delay line calibration method based on time-domain reflection technology has been designed.Through multiple sets of comparative experiments,the measurement result deviation is less than 50 ps,and the delay line meets the on-site measurement requirements of the testing system.

关 键 词：传输延迟 标准延迟线 定值 集成电路 

分 类 号：TB973[一般工业技术—计量学]