基于Cerebrus的Genus+Innovus流程的功耗面积优化  

Power consumption area optimization for the Cerebrus-based Genus+Innovus procedure

作　　者：汪锋刚 晋亚紧 周国华 刘宇峥 Wang Fenggang;Jin Yajin;Zhou Guohua;Liu Yuzheng(Department of Back-End Design,Sanechips Technology Co.,Ltd.,Shenzhen 518055,China;State Key Laboratory of Mobile Network and Mobile Multimedia Technology,Shenzhen 518055,China;Cadence Design Systems,Inc.,Shanghai 200120,China)

机构地区：[1]深圳市中兴微电子技术有限公司后端设计部,广东深圳518055 [2]移动网络和移动多媒体技术国家重点实验室,广东深圳518055 [3]上海楷登电子科技有限公司,上海200120

出　　处：《电子技术应用》2024年第8期21-25,共5页Application of Electronic Technique

摘　　要：对于性能功耗面积(PPA)的追求已成为IC芯片设计的共识,尤其是发展到先进工艺节点,PPA已成为IC设计综合性能的重要指标,尤其是对于大型SoC芯片中clone很多次的模块,对于PPA的追求变得更加极致。介绍了基于Cadence公司的Genus工具和Cerebrus工具,通过综合阶段与后端PR各个阶段的优化,共同提升PPA的优化方案。最终结果显示,在时序及DRC基本收敛的情况下,使用Cerebrus工具相比Innovus可以使功耗降低3.5%,面积降低3.1%,使用Genus+Innovus流程可以使功耗降低6.4%,面积降低8.5%,极大地降低了芯片的面积及功耗。The pursuit of performance,power and area(PPA)has become the consensus of IC chip design,especially the development to advanced process nodes.PPA has become a crucial metric of overall performance of IC design.Especially for the modules cloned numerous times in large-scale SoC chips,the pursuit of PPA becomes more extreme.This document describes how to improve the PPA optimization solution based on the Genus and Cerebrus tools of Cadence and the optimization of the Synthesis and the Back-End PR stage.The final result shows that,under the convergence of timing and DRC,employing the Cerebrus tool compared to Innovus can reduce power by 3.5%and area by 3.1%.Furthermore,utilizing the Genus+Innovus flow can reduce power by 6.4%and area by 8.5%,significantly decreasing chip area and power.

关 键 词：芯片设计 Genus工具 Cerebrus工具 PPA优化 

分 类 号：TN402[电子电信—微电子学与固体电子学]