使用Cadence AI技术加速验证效率提升  

Accelerating verification efficiency with Cadence AI technology

作　　者：徐加山 姚舒雨 徐志磊 Xu Jiashan;Yao Shuyu;Xu Zhilei(Shenzhen Sanechips Technology Co.,Ltd.,Nanjing 210012,China;Cadence Design Systems,Inc.,Shanghai 200120,China)

机构地区：[1]深圳市中兴微电子技术有限公司,江苏南京210012 [2]上海楷登电子科技有限公司,上海200120

出　　处：《电子技术应用》2024年第8期32-36,共5页Application of Electronic Technique

摘　　要：随着硬件设计规模和复杂程度的不断增加,验证收敛的挑战难度不断增大,单纯依靠增加CPU核数量并行测试的方法治标不治本。如何在投片前做到验证关键指标收敛,是验证工程师面对的难题。为解决这一难题,提出了采用人工智能驱动的验证EDA工具和生成式大模型两种提效方案,其中EDA工具有Cadence利用人工智能驱动的Verisium apps和采用机器学习技术Xcelium ML,前者用来提升验证故障定位效率,包括Verisium AutoTriage、Verisium SemanticDiff、Verisium WaveMiner等,后者可用来提升验证覆盖率收敛效率。生成式大模型可辅助智能debug和自动生成验证用例,主要介绍各实现方案,并给出了项目实验提升结果。With the increasing scale and complexity of hardware design,the verification convergence challenge is becoming more difficult.Simply increasing the number of CPU cores to increase parallel testing cannot solve this problem fundamentally.How to achieve verification convergence before tape-out is a difficult problem that verification engineers have to face.To solve this problem,this article proposes two efficiency improvement solutions:AI-driven verification EDA tools and large-scale model generation.The EDA tools include Cadence's AI-driven Verisium apps and Xcelium ML using machine learning technology.The former is used to improve the fault location efficiency of verification,including Verisium AutoTriage,Verisium SemanticDiff,and Verisium WaveMiner.The latter can be used to improve the verification coverage convergence efficiency.Large-scale model generation can assist intelligent debugging and automatically generate verification cases.This article mainly introduces each implementation solution and gives the project experimental improvement results.

关 键 词：IC验证 人工智能 Verisium apps 效率提升 

分 类 号：TN402[电子电信—微电子学与固体电子学]