高速时钟信号的测试点选择与分析  

Test Point Selection and Analysis of High Speed Clock Signal

作　　者：张子春 刘婷婷 杨开泰 Zhang Zichun;Liu Tingting;Yang Kaitai(Aeronautics Computing Technology Research Institute,Xi’an Shaanxi 710065,China)

机构地区：[1]中国航空工业集团公司西安航空计算技术研究所,陕西西安710065

出　　处：《山西电子技术》2024年第4期40-42,107,共4页Shanxi Electronic Technology

摘　　要：为了实现对高速时钟信号质量的精确判别,在分析传输线阻抗匹配原理基础上,深入分析传输线反射对时钟信号质量以及传输时延的影响。以PCIE的一对参考时钟信号为例,进行时钟信号传输链路的建模仿真,通过对晶振源端pin脚以及终端匹配电阻pin脚信号仿真测试波形的对比,发现终端匹配电阻pin处时钟信号单调性更好,因此提出高速时钟信号最佳选择终端匹配电阻pin脚的测试点,以减小传输线发射对信号的影响,便于后续产品的调试生产。In order to achieve accurate discrimination of high-speed clock signal quality,this paper analyzes the influence of transmission line reflection on clock signal quality and transmission delay based on the analysis of transmission line impedance matching principle.Taking a pair of PCIE reference clock signals as an example,modeling and simulation of clock signal transmission link are carried out.Compared the signal at the pin of crystal oscillator with the signal at the pin of terminal resistance,it is found that the monotone of the clock signal at the terminal matching resistance pin is better.Therefore,it is proposed that the test point of the terminal matching resistance pin is the best choice for high-speed clock signal,so as to reduce the impact of transmission line reflection and facilitate the debugging and production of products.

关 键 词：时钟信号测试 传输线反射 测试点 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术] TN9[电子电信—信息与通信工程]