基于FPGA的OFDM采样时钟同步设计  

Design of OFDM Sampling Clock Synchronization Based on FPGA

作　　者：龚莹 GONG Ying(The 27th Research Institute of China Electronics Technology Group Corporation,Zhengzhou 450047,China)

机构地区：[1]中国电子科技集团公司第二十七研究所,郑州450047

出　　处：《电光系统》2024年第2期49-55,共7页Electronic and Electro-optical Systems

摘　　要：相比于传统的逻辑电路和门阵列,FPGA具有可重复编程、低功耗、低延时等优点。OFDM技术具有抗衰落能力强、频率利用率和频谱效率高以及对多径效应的鲁棒性强等优点,适合高速数据传输且易于实现,在现代无线通信系统中得到了广泛的应用。在OFDM技术中,接收机同步技术对于系统的通信质量有很重要的影响,该同步技术主要包括定时同步、载波频率同步和采样时钟同步三个部分,其中采样时钟同步的目的在于消除接收端A/D采样的频率、相位与发送端的D/A时钟频率以及相位的偏差对系统性能的影响,为了补偿采样频率偏移,在经过FFT后,利用导频信号在频域进行校正,最后基于FPGA设计采样时钟同步模块,主要包括导频提取和数据缓存、导频相关、频偏估计、频偏补偿和顺序调整5个部分。Compared with traditional logic circuits and gate arrays,FPGA has the advantages of repeatable pro-gramming,low power and low latency.OFDM technology has the advantages of strong anti-fading ability,high frequency utilization and spectral efficiency,and strong robustness to multipath effects.It is suitable for high-speed data transmission and easy to implement.It has been widely used in modern wireless communication sys-tems.In OFDM technology,receiver synchronization technology has a very important influence on the communi-cation quality of the system.The synchronization technology mainly includes three parts:timing synchroniza-tion,carrier synchronization and sampling clock synchronization.The purpose of sampling clock synchronization is to eliminate the influence of the frequency and phase of A/D sampling at the receiving end and the D/A clock frequency and phase deviation at the transmitting end on the system performance.In order to compensate the sampling frequency offset,after FFT,the pilot signal is used to correct in the frequency domain.Finally,the sampling clock synchronization module is designed based on FPGA.It mainly includes five parts:pilot extrac-tion and data caching,pilot correlation,frequency offset estimation,frequency offset compensation and se-quence adjustment.

关 键 词：OFDM技术 接收机同步 采样时钟同步FPGA 

分 类 号：TN791[电子电信—电路与系统]