低抖动电荷泵锁相环设计及其Simulink建模仿真  

Design of Low jitter Charge Pump Phase locked Loop and Modeling Simulation in Simulink

作　　者：蔡俊[1] 王勇 CAI Jun;WANG Yong(School of Electrical and Information Engineering,Anhui University of Science and Technology,Huainan 232001,China)

机构地区：[1]安徽理工大学电气与信息工程学院,安徽淮南232001

出　　处：《宜春学院学报》2024年第6期28-34,共7页Journal of Yichun University

基　　金：安徽省自然科学基金项目(编号:2108085MF200);安徽高校自然科学重点项目(编号:KJ2020A0307)。

摘　　要：随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。With the advancement of integrated circuit technology,the working frequency of circuits is becoming higher and higher,which also puts forward higher requirements for clock signal jitter and phase noise.In response to the problems of multiple parameters,complex structure,and long transient simulation time in the phase locked loop circuit,a mathematical model of the charge pump phase locked loop system is established,and MATLAB/Simulink is used to model the negative feedback system,achieving rapid dynamic simulation of the charge pump phase locked loop.The circuit design,layout,physical verification,and extraction of parasitic parameters and post simulation of the phase locked loop were completed,and a low jitter charge pump phase locked loop with a typical value of input frequency of 30 MHz and a locking frequency of 1.5 GHz was designed in TSMC 65 nm CMOS process.The post simulation results show that the PLL circuit has a good performance index,under typical value,the PLL has a lock up time of 10μs,peak to peak jitter of 2.68 ps during lockup,a clock signal duty cycle of 45%.

关 键 词：锁相环 鉴相鉴频器 电荷泵 压控振荡器 

分 类 号：TN432[电子电信—微电子学与固体电子学]