检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:钟怀 谢子成 唐立军[1] ZHONG Huai;XIE Zicheng;TANG Lijun(School of Physics&Electronic Science,Changsha University of Science&Technology,Changsha 410114,China)
机构地区:[1]长沙理工大学物理与电子科学学院,湖南长沙410114
出 处:《电子设计工程》2024年第18期114-118,共5页Electronic Design Engineering
基 金:湖南省水利科技项目(XSKJ2019081-44)。
摘 要:H.265视频编解码通常用于超高清视频,但由于数据量大,编解码算法复杂,会导致较大的视频端到端传输时延。该文提出了一种针对4K视频流H.265编解码的低时延解决方案,采用同步机制的异构多核ARM+FPGA架构,在RAM端搭建Linux操作系统实现多任务处理和实时监控,在FPGA端实现并行加速的H.265编码格式。利用该方案对4K@60 Hz,像素格式YCbCr 4∶2∶0,颜色深度8 bits的视频进行测试。测试结果显示,端到端时延仅为29.5 ms,其中捕获时间为2 ms,编码时间为5 ms,解码时间为10 ms,显示时间为12.5 ms,传输速度提高了45.5%。通过比较分析,该方法在保证高压缩率的情况下,具有低时延传输的明显优势。H.265 video codec is usually used for ultra HD videos.However,due to the large amount of data and complex codec algorithm,the end-to-end video transmission delay is relatively large.In this paper,a low latency solution for 4K video stream H.265 codec is proposed.A heterogeneous multi-core ARM+FPGA architecture based on synchronous mechanism is adopted.Linux operating system is built on the RAM side to realize multitasking and real-time monitoring,and parallel accelerated H.265 encoding format is implemented on the FPGA side.This scheme is used to test the video with 4K@60 Hz,pixel format YCbCr 4∶2∶0 and color depth of 8 bits.Test results show that the end-to-end delay is only 29.5 ms,including capture time of 2 ms,encoding time of 5 ms,decoding time of 10 ms,display time of 12.5 ms,transmission speed increased by 45.5%.Through comparative analysis,this method has the obvious advantage of low latency transmission under the condition of guaranteeing high compression rate.
关 键 词:同步机制 低时延 H.265 4K视频流 异构多核
分 类 号:TN919.81[电子电信—通信与信息系统]
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:216.73.216.7