基于FPGA的异步FIFO缓存数据溢出控制系统  

Data Overflow Control System of Asynchronous FIFO Buffer Based on FPGA

作　　者：张伟 Zhang Wei(College of Intelligence,Xi’an Aeronautical Polytechnic Institute,Xi’an 710089,China)

机构地区：[1]西安航空职业技术学院人工智能学院,西安710089

出　　处：《兵工自动化》2024年第9期55-58,65,共5页Ordnance Industry Automation

摘　　要：为获取更高效、稳定的缓存数据控制方法,设计基于现场可编程门阵列(field programmable gate array,FPGA)的异步FIFO缓存数据溢出控制系统。设计存储控制方案,得到基于FPGA的系统硬件;建立缓存数据存储溢出模型,得到数据节点剩余能量的最小值最大化求解,在函数模型下判断存储数据是否溢出;设计数据溢出控制算法,得到缓存数据溢出控制系统的软件。分别对数据溢出的监测性能与控制性能进行测试。实验结果表明:使用该方法剩余的能耗较高,可见该方法对于缓存数据的监测与控制性能均较好。In order to obtain a more efficient and stable cache data control method,an asynchronous FIFO cache data overflow control system based on field programmable gate array(FPGA)is designed.A storage control scheme is designed to obtain the system hardware based on FPGA;a cache data storage overflow model is established to obtain the maximum solution of the minimum value of the residual energy of the data node,and the storage data is judged whether to overflow under the function model;a data overflow control algorithm is designed to obtain the software of the cache data overflow control system.The monitoring performance and control performance of data overflow are tested respectively,and the experimental results show that the remaining energy consumption of this method is higher,which shows that this method has good monitoring and control performance for cache data.

关 键 词：FPGA 异步FIFO存储器 缓存数据 数据溢出控制 存储控制 数据节点 

分 类 号：TN06[电子电信—物理电子学]